BTC instruction

1. Mai Dian mall is not a virtual currency on the Internet. It's like a mall. It's said to be a pyramid selling mall
network virtual currency generally includes game currency and digital currency
digital currency generally refers to bitcoin, Leyte coin, dogcoin and project crowdfunding token of European crowdfunding platform.

2. Imtoken doesn't have BTC wallet, it can only store erc20 token

4. BT instruction

format: BT OPD, OPS
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function: the bits specified by source ops in destination OPD are sent to CF flag
note: 1. In instruction, destination OPD can only be 16 / 32-bit general-purpose register or storage unit, which is used to specify the data to be tested; The source operands OPS must be 8-bit immediate or 16 / 32-bit general-purpose registers with the same length as the destination operands, which are used to specify the bits to be tested. If the destination operands are registers, the remainder of the source operands divided by 16 / 32 is the bits to be tested, which is between 0-15 / 31.

2; EAX=12345678H

BT EAX,5 ; D5 bit of eax = 1 -- & gt; CF, eax = 12345678h

note: if the destination operand is a storage unit, then the lowest bit of the unit is 0. Increment from the lowest bit to each bit at the high end of the address and decrement to each bit at the low end of the address. This part of memory data is a 2g-1 ~ - 2G bit string, The signed source operands indicate the bits to be tested

5. From bitcoin to Ethereum, it seems that more and more institutional traders are interested in accumulating Ethereum for long-term benefits, because Ethereum is also a store of value

1. Ethereum: a better value accumulation target

for many years, accumulating bitcoin has been the main way to store the value of cryptocurrency. Investors use bitcoin as a sharp weapon against the economic crisis. However, institutional traders are now also interested in Ethereum

in the 2020 annual review report of coinbase, it is noted that institutional customers are more and more interested in Ethereum. The reason is related to how investors evaluate Ethereum ecosystem

first of all, it is the original currency of the network. Because Ethereum is a platform for many valuable projects, Ethereum has become a powerful trading currency in Ethereum ecosystem

Why are more and more institutional traders hoarding Ethereum

the report points out that the driving force for Ethereum holders to invest comes from: first, Ethereum's potential as a value store is constantly developing; 2、 Ethereum's status as a digital currency provides the basis for its network transactions<

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2. Investment institutions such as coinbase and Gemini are optimistic about Ethereum and defi

Arthur Cheong, founder of definance capital and portfolio manager focusing on defi encryption fund, pointed out in a statement in coindesk, "I think bold investors will explore Ethereum and defi after studying bitcoin."

according to the data, some investment institutions such as coinbase and Gemini are incredibly bullish on Ethereum. In addition, more and more large investors are looking for different decentralized financing space

Why are more and more institutional traders hoarding Ethereum< However, deniss vinokourou, a digital asset investment manager, believes that "not everyone is satisfied with the risks associated with defi that still exist, but the rapid growth of active projects in Ethereum supports capital appreciation."

unlike bitcoin, Ethereum has many ways to retain investors and lock them in for a long time. After the release of eth2.0, Ethereum owners have made a lot of profits in long Ethereum

the original text is from ambcrypto and compiled by blockchain knight. The right in English belongs to the original author. If you want to reprint it in Chinese, please contact the compiler.

6. CPU extended instruction set CPU relies on instructions to calculate and control the system. Each CPU is designed with a series of instruction systems that match its hardware circuit. Instruction set is one of the most effective tools to improve the efficiency of microprocessor. From the current mainstream architecture, instruction set can be divided into complex instruction set and reced instruction set. From the specific application, such as Intel's MMX (multi media extended), SSE, SSE2 (streaming single instruction multiple data extensions 2), see3 and AMD's 3DNOW! These are the extended instruction sets of CPU, which enhance the processing ability of multimedia, graphics and Internet. We usually refer to the extended instruction set of CPU as the instruction set of CPU. Sse3 instruction set is also the smallest instruction set at present. Previously, MMX contained 57 commands, SSE contained 50 commands, SSE2 contained 144 commands, and sse3 contained 13 commands. At present, sse3 is also the most advanced instruction set. Intel Prescott processor already supports sse3 instruction set. AMD will add support for sse3 instruction set to al core processor in the future, and quanmeida processor will also support this instruction set<

instruction set:
(1) to know what instruction set is, we should start with the CPU of x86 architecture. The x86 instruction set is specially developed by Intel for its first 16 bit CPU (i8086). The CPU of the world's first PC, i8088 (simplified version of i8086), which was launched by IBM in 1981, also uses the x86 instruction. At the same time, in order to improve the floating-point data processing ability, the data coprocessor of the x87 chip family added to the computer uses the x87 instruction, Later, the x86 instruction set and the x87 instruction set are collectively referred to as the x86 instruction set. With the continuous development of CPU technology, Intel has developed updated i80386 and i80486 until today. However, in order to ensure that computers can continue to run all kinds of applications developed in the past to protect and inherit rich software resources, all CPUs proced by Intel still continue to use x86 instruction set, so their CPUs still belong to x86 series. Because Intel x86 series and its compatible CPUs all use x86 instruction set, today's huge lineup of X86 series and compatible CPUs has been formed
(2) RISC instruction set RISC instruction set is the future development direction of high performance CPU. It is opposite to the traditional CISC (complex instruction set). In contrast, RISC has a unified instruction format, fewer types, and fewer addressing modes than complex instruction sets. Of course, the processing speed is much faster. The RISC instruction set is also compatible with the original x86 instruction set.

7. 1. General data transfer instruction.
mov transfers word or byte.
movsx extends symbol first, then transfers.
movzx extends zero first, then transfers.

movsx reg16, R / M8; o16 0F BE /r [386]
MOVSX reg32,r/m8 ; o32 0F BE /r [386]
MOVSX reg32,r/m16 ; o32 0F BF /r [386]

MOVZX reg16,r/m8 ; o16 0F B6 /r [386]
MOVZX reg32,r/m8 ; o32 0F B6 /r [386]
MOVZX reg32,r/m16 ; O320f B7 / R [386]

push pushes the word into the stack.
pop pops the word out of the stack.
pusha pushes ax, CX, DX, BX, SP, BP, Si, di into the stack in turn.
PopA pushes Di, Si, BP, SP, BX, DX, CX, ax out of the stack in turn.
PUSHAD pushes eax, ECX, EDX, ebx, esp, EBP, ESI, EDI is pushed into the stack in turn.
POPAD pops EDI, ESI, EBP, esp, ebx, EDX, ECX, eax out of the stack in turn.
bswap switches the order of bytes in 32-bit registers.
xchg switches words or bytes. (at least one of the operands is a register, Segment registers cannot be used as operands)
cmpxchg compares and exchanges operands. (the second operand must be accumulator Al / ax / eax)
xadd exchanges first and then accumulates. (the result is in the first operand)
xlat byte table lookup conversion.
- BX points to the starting point of a 256 byte table, Al is the index value of the table (0-255,
0-ffh); Return Al as the result of table lookup ([BX + al] - & gt; Al)
2. I / O port transmit instruction.
in I / O port input. (Syntax: in accumulator, {port number │ DX})
out I / O port output. (Syntax: out {port number │ DX}), accumulator)
when I / O port is specified by immediate mode, its range is 0-255; When specified by register DX,
its range is 0-65535.
3. Destination address transfer instruction.
lea loads the valid address.
example: lea DX, string; Save the offset address to DX.
LDS transfers the target pointer and loads the pointer content into DS.
example: LDS, Si, string; Save the segment address: offset address to ds: Si.
Les transfers the target pointer, and loads the pointer content into es.
example: les, Di, string; Save the segment address: offset address to es: di.
LFS transfers the target pointer and loads the pointer content into FS.
example: LFS, Di, string; Save the segment address: offset address to FS: di.
LGS transfers the target pointer and loads the pointer content into GS.
example: LGS, Di, string; Save the segment address: offset address to GS: di.
LSS transmits the target pointer and loads the pointer content into SS.
example: LSS, Di, string; Save the segment address: offset address to SS: di.
4. Flag transfer instruction.
lahf flag register transfer, load the flag into ah.
SAHF flag register transfer, Load the ah content into the flag register.
pushf flag is put on the stack.
POPF flag is put on the stack.
pushd 32-bit flag is put on the stack.
POPD 32-bit flag is put on the stack.

II Arithmetic instruction
add add.
ADC add with carry.
Inc add 1.
ASCII adjustment of AAA add.
decimal adjustment of DAA add.
sub subtraction.
SBB subtract with borrow.
Dec subtract 1.
NEC negate (subtract by 0). < br />CMP comparison. (two operands are subtracted, only the flag bit is modified, and the result is not returned)
ASCII adjustment of AAS subtraction.
decimal adjustment of Das subtraction.
mul unsigned multiplication.
imul integer multiplication.
ah and Al (byte operation), or DX and ax (word operation) are returned,
adjust the ASCII code of AAM multiplication.
div unsigned division.
IDIV integer division.
the above two results are returned:
quotient returns Al, remainder returns ah, (byte operation)
or quotient returns ax, remainder returns DX, (word operation)
adjustment of ASCII code for aad division.
Convert CBW bytes to words. (extend symbols of bytes in Al to ah)
Convert CWD words to doublewords. (extend symbols of words in ax to DX)
Convert CWDE words to doublewords. (extend symbols of words in ax to eax)
Expand CDQ doublewords (extend the symbol of words in eax to EDX)

3. Logic operation instruction
and operation.
or operation.
XOR operation.
not negate.
test test. (two operands operate and, only modify flag bit, No return result)
SHL logic shift left.
Sal arithmetic shift left. (= SHL)
SHR logic shift right.
SAR arithmetic shift right. (= SHR)
rol cycle shift left.
ror cycle shift right.
RCL shift left through carry cycle.
RCR shift right through carry cycle.
the results of SHL shift left For the above eight shift instructions, the number of shifts can be up to 255 times.
when shifting once, the opcode can be directly used. For example, SHL ax, 1.
shift & gt; For example, MOV Cl, 04
SHL ax, CL

four String instruction
ds: Si source string segment register: source string index.
es: Di target string segment register: target string index.
CX repeat counter.
Al / ax scan value.
d flag 0 indicates that Si and di should be incremented automatically ring repeat operation; The Z flag is used to control the end of the scan or compare operation.
MOVs string transfer.
(MoVSb transfer character. Movsw transfer word. Movsd transfer double word.)
CMPs string comparison.
(cmpsb compare character. Cmpsw compare word.)
SCAs string scan.
/>Compare the content of Al or ax with the target string, The comparison result is reflected in the flag bit.
LODs loads the string.
loads the elements (words or bytes) in the source string into Al or ax one by one.
(lodsb transmits characters. Lodsw transmits words. Lodsd transmits doublewords.)
STOs saves the string.
is the reverse process of LODs.
rep when CX / ECX & lt& gt; 0.
repe / repz when ZF = 1 or the comparison results are equal, and CX / ECX & lt& gt; 0.
repne / repnz when ZF = 0 or the comparison results are not equal, and CX / ECX & lt& gt; When CF = 1 and CX / ECX & lt& gt; When CF = 0 and CX / ECX & lt& gt; 5. Program transfer instructions
1 & gt; Unconditional transfer instruction (long transfer)
JMP unconditional transfer instruction
call procere call
RET / retf procere return.
2 & gt; Conditional transfer instruction (short transfer, within the distance from - 128 to + 127)
(if and only if (SF XOR of) = 1, OP1 JA / JNBE is not less than or equal to transfer.
Jae / JNB is greater than or equal to transfer.
JB / jnae is less than transfer.
JBE / JNA is less than or equal to transfer.
the above four, Test the result of signed integer operation (flag C and z)
JG / jnle is greater than transition.
jge / JnL is greater than or equal to transition.
JL / jnge is less than transition.
JLE / JNG is less than or equal to transition.
above four items, test the result of signed integer operation (flag s, When jne / JNZ is not equal to transfer.
JC transfers with carry.
JNC transfers without carry.
jno transfers without overflow.
JNP / JPO transfers with odd parity.
JNS sign bit is & quot; 0" Time transition.
Jo overflow transition.
transition when JP / JPE parity is even.
JS symbol bit is & quot; 1"
3 & gt; Loop control command (short transfer)
loop CX is not zero.
loop / loopz CX is not zero and flag z = 1.
loop Ne / loopnz CX is not zero and flag z = 0.
jcxz CX is zero.
jecxz ECX is zero.
4 & gt; Interrupt instruction
int interrupt instruction
into overflow interrupt
IRET interrupt return
5 & gt; Processor control instruction
HLT processor pause, When the chip lead test is high, the CPU will enter the waiting state.
ESC switches to the external processor.
lock blocks the bus.
NOP null operation.
STC set carry flag.
CLC clear carry flag.
CMC carry flag Flag reverse.
STD set direction flag.
CLD clear direction flag.
STI set interrupt permission.
cli clear interrupt permission.

VI Pseudo instruction
DW definition word (2 bytes).
proc definition process.
end process.
segment definition segment.
establish segment register addressing.
ends segment.
end program.

seven bit operation instruction, Processor control instruction
1. Bit operation instruction, a new set of instructions in 8086, including bit test and bit scan. BT, BTC, BTR, BTS, BSF, BSR
1.1 BT (bit test), bit test instruction, instruction format:
BT OPRD1, oprd2, rule: OPRD1 can be a 16 bit or 32-bit general-purpose register or storage unit. Oprd2 must be an 8-bit immediate or a general-purpose register of the same length as OPRD1. If oprd2 is divided by OPRD1, assuming the quotient is stored in div and the remainder is stored in mod, then mod is the bit number to test OPRD1 operands. Its main function is to send the value of the bit to be tested to cf. take a few simple examples:
1.2 BTC (bit test and complexity). The usage and rules of testing and negating are the same as BT, but the functions are different, It not only sends the value of the bit to be tested to CF, but also reverses the bit< br />1.3 BTR(Bit Test And Reset)，

8.

NOP instruction, also known as "null instruction", in x86 CPU, machine code is 0x90 (144)

NOP does not perform the operation, but takes one program step. When executing NOP, you don't do anything. Sometimes you can use NOP instruction to short some contacts or use NOP instruction to cover unwanted instructions. When the PLC executes the operation of clearing the user memory, all the contents of the user memory become empty

The

NOP instruction belongs to PLC instruction, which will occupy the CPU time slice to execute an instruction. It is often used for program delay or precise timing, but it is not obvious on faster CPU

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extended data:

transfer instruction:

1, including general data transfer instruction MOV, conditional transfer instruction cmovcc, stack operation instruction push / push / push / Pop / PopA / POPAD, exchange instruction xchg / xlat / bswap, address or segment descriptor selection sub transfer instruction lea / LDS / LES / LFS / LGS / LSS, etc

logic operations:

1. These instructions are used to perform arithmetic and logic operations, including add instruction add / ADC, subtract instruction sub / SBB, add instruction Inc, subtract instruction Dec, compare instruction CMP, multiply instruction mul / imul

Division instruction div / IDIV, symbol extension instruction CBW / CWDE / cdqe, decimal adjustment instruction DAA / Das / AAA / AAS, logic operation instruction not / and / or / XOR / test, etc

shift instructions:

1. This part of instructions is used to move the register or memory operands a specified number of times. It includes logical shift left instruction SHL, logical shift right instruction SHR, arithmetic shift left instruction Sal, arithmetic shift right instruction SAR, cyclic shift left instruction rol, cyclic shift right instruction ror, etc

bit operation:

1. These instructions include bit test instruction BT, bit test and set instruction BTS, bit test and reset instruction BTR, bit test and reverse instruction BTC, bit forward scan instruction BSF, bit backward scan instruction BSR, etc

9. No, the lock instruction prefix can only be used for the following instructions:
add, ADC, and, BTC, BTR, BTS, cmpxchg, cmpxch8b, Dec, Inc, neg, not, or, SBB, sub, XOR, xadd, xchg

the lock instruction will change the instruction into an atomic instruction only when the target operand is a memory address; If the destination operand is not memory, a UD (undefined opcode) error is generated

in addition, it should be noted that some compilers will legally compile the lock instruction before the instruction mentioned above (for example, lock mov [data], eax), but will also generate UD errors when running the program

digression: when one of the operands of xchg is memory, the lock instruction will be inserted automatically, which makes the required cycle very long.