BTC assembly
format: BT OPD, OPS
-
function: the bits specified by source ops in destination OPD are sent to CF flag
note: 1. In instruction, destination OPD can only be 16 / 32-bit general-purpose register or storage unit, which is used to specify the data to be tested; The source operands OPS must be 8-bit immediate or 16 / 32-bit general-purpose registers with the same length as the destination operands, which are used to specify the bits to be tested. If the destination operands are registers, the remainder of the source operands divided by 16 / 32 is the bits to be tested, which is between 0-15 / 31.
2; EAX=12345678H
BT EAX,5 ; D5 bit of eax = 1 -- & gt; CF, eax = 12345678h
note: if the destination operand is a storage unit, then the lowest bit of the unit is 0. Increment from the lowest bit to each bit at the high end of the address and decrement to each bit at the low end of the address. This part of memory data is a 2g-1 ~ - 2G bit string, The signed source operands indicate the bits to be tested
instruction set:
(1) to know what instruction set is, we should start with the CPU of x86 architecture. The x86 instruction set is specially developed by Intel for its first 16 bit CPU (i8086). The CPU of the world's first PC, i8088 (simplified version of i8086), which was launched by IBM in 1981, also uses the x86 instruction. At the same time, in order to improve the floating-point data processing ability, the data coprocessor of the x87 chip family added to the computer uses the x87 instruction, Later, the x86 instruction set and the x87 instruction set are collectively referred to as the x86 instruction set. With the continuous development of CPU technology, Intel has developed updated i80386 and i80486 until today. However, in order to ensure that computers can continue to run all kinds of applications developed in the past to protect and inherit rich software resources, all CPUs proced by Intel still continue to use x86 instruction set, so their CPUs still belong to x86 series. Because Intel x86 series and its compatible CPUs all use x86 instruction set, today's huge lineup of X86 series and compatible CPUs has been formed
(2) RISC instruction set RISC instruction set is the future development direction of high performance CPU. It is opposite to the traditional CISC (complex instruction set). In contrast, RISC has a unified instruction format, fewer types, and fewer addressing modes than complex instruction sets. Of course, the processing speed is much faster. The RISC instruction set is also compatible with the original x86 instruction set.
mov transfers word or byte.
movsx extends symbol first, then transfers.
movzx extends zero first, then transfers.
movsx reg16, R / M8; o16 0F BE /r [386]
MOVSX reg32,r/m8 ; o32 0F BE /r [386]
MOVSX reg32,r/m16 ; o32 0F BF /r [386]
MOVZX reg16,r/m8 ; o16 0F B6 /r [386]
MOVZX reg32,r/m8 ; o32 0F B6 /r [386]
MOVZX reg32,r/m16 ; O320f B7 / R [386]
push pushes the word into the stack.
pop pops the word out of the stack.
pusha pushes ax, CX, DX, BX, SP, BP, Si, di into the stack in turn.
PopA pushes Di, Si, BP, SP, BX, DX, CX, ax out of the stack in turn.
PUSHAD pushes eax, ECX, EDX, ebx, esp, EBP, ESI, EDI is pushed into the stack in turn.
POPAD pops EDI, ESI, EBP, esp, ebx, EDX, ECX, eax out of the stack in turn.
bswap switches the order of bytes in 32-bit registers.
xchg switches words or bytes. (at least one of the operands is a register, Segment registers cannot be used as operands)
cmpxchg compares and exchanges operands. (the second operand must be accumulator Al / ax / eax)
xadd exchanges first and then accumulates. (the result is in the first operand)
xlat byte table lookup conversion.
- BX points to the starting point of a 256 byte table, Al is the index value of the table (0-255,
0-ffh); Return Al as the result of table lookup ([BX + al] - & gt; Al)
2. I / O port transmit instruction.
in I / O port input. (Syntax: in accumulator, {port number │ DX})
out I / O port output. (Syntax: out {port number │ DX}), accumulator)
when I / O port is specified by immediate mode, its range is 0-255; When specified by register DX,
its range is 0-65535.
3. Destination address transfer instruction.
lea loads the valid address.
example: lea DX, string; Save the offset address to DX.
LDS transfers the target pointer and loads the pointer content into DS.
example: LDS, Si, string; Save the segment address: offset address to ds: Si.
Les transfers the target pointer, and loads the pointer content into es.
example: les, Di, string; Save the segment address: offset address to es: di.
LFS transfers the target pointer and loads the pointer content into FS.
example: LFS, Di, string; Save the segment address: offset address to FS: di.
LGS transfers the target pointer and loads the pointer content into GS.
example: LGS, Di, string; Save the segment address: offset address to GS: di.
LSS transmits the target pointer and loads the pointer content into SS.
example: LSS, Di, string; Save the segment address: offset address to SS: di.
4. Flag transfer instruction.
lahf flag register transfer, load the flag into ah.
SAHF flag register transfer, Load the ah content into the flag register.
pushf flag is put on the stack.
POPF flag is put on the stack.
pushd 32-bit flag is put on the stack.
POPD 32-bit flag is put on the stack.
II Arithmetic instruction
add add.
ADC add with carry.
Inc add 1.
ASCII adjustment of AAA add.
decimal adjustment of DAA add.
sub subtraction.
SBB subtract with borrow.
Dec subtract 1.
NEC negate (subtract by 0). < br />CMP comparison. (two operands are subtracted, only the flag bit is modified, and the result is not returned)
ASCII adjustment of AAS subtraction.
decimal adjustment of Das subtraction.
mul unsigned multiplication.
imul integer multiplication.
ah and Al (byte operation), or DX and ax (word operation) are returned,
adjust the ASCII code of AAM multiplication.
div unsigned division.
IDIV integer division.
the above two results are returned:
quotient returns Al, remainder returns ah, (byte operation)
or quotient returns ax, remainder returns DX, (word operation)
adjustment of ASCII code for aad division.
Convert CBW bytes to words. (extend symbols of bytes in Al to ah)
Convert CWD words to doublewords. (extend symbols of words in ax to DX)
Convert CWDE words to doublewords. (extend symbols of words in ax to eax)
Expand CDQ doublewords (extend the symbol of words in eax to EDX)
3. Logic operation instruction
and operation.
or operation.
XOR operation.
not negate.
test test. (two operands operate and, only modify flag bit, No return result)
SHL logic shift left.
Sal arithmetic shift left. (= SHL)
SHR logic shift right.
SAR arithmetic shift right. (= SHR)
rol cycle shift left.
ror cycle shift right.
RCL shift left through carry cycle.
RCR shift right through carry cycle.
the results of SHL shift left For the above eight shift instructions, the number of shifts can be up to 255 times.
when shifting once, the opcode can be directly used. For example, SHL ax, 1.
shift & gt; For example, MOV Cl, 04
SHL ax, CL
four String instruction
ds: Si source string segment register: source string index.
es: Di target string segment register: target string index.
CX repeat counter.
Al / ax scan value.
d flag 0 indicates that Si and di should be incremented automatically ring repeat operation; The Z flag is used to control the end of the scan or compare operation.
MOVs string transfer.
(MoVSb transfer character. Movsw transfer word. Movsd transfer double word.)
CMPs string comparison.
(cmpsb compare character. Cmpsw compare word.)
SCAs string scan.
/>Compare the content of Al or ax with the target string, The comparison result is reflected in the flag bit.
LODs loads the string.
loads the elements (words or bytes) in the source string into Al or ax one by one.
(lodsb transmits characters. Lodsw transmits words. Lodsd transmits doublewords.)
STOs saves the string.
is the reverse process of LODs.
rep when CX / ECX & lt& gt; 0.
repe / repz when ZF = 1 or the comparison results are equal, and CX / ECX & lt& gt; 0.
repne / repnz when ZF = 0 or the comparison results are not equal, and CX / ECX & lt& gt; When CF = 1 and CX / ECX & lt& gt; When CF = 0 and CX / ECX & lt& gt; 5. Program transfer instructions
1 & gt; Unconditional transfer instruction (long transfer)
JMP unconditional transfer instruction
call procere call
RET / retf procere return.
2 & gt; Conditional transfer instruction (short transfer, within the distance from - 128 to + 127)
(if and only if (SF XOR of) = 1, OP1 JA / JNBE is not less than or equal to transfer.
Jae / JNB is greater than or equal to transfer.
JB / jnae is less than transfer.
JBE / JNA is less than or equal to transfer.
the above four, Test the result of signed integer operation (flag C and z)
JG / jnle is greater than transition.
jge / JnL is greater than or equal to transition.
JL / jnge is less than transition.
JLE / JNG is less than or equal to transition.
above four items, test the result of signed integer operation (flag s, When jne / JNZ is not equal to transfer.
JC transfers with carry.
JNC transfers without carry.
jno transfers without overflow.
JNP / JPO transfers with odd parity.
JNS sign bit is & quot; 0" Time transition.
Jo overflow transition.
transition when JP / JPE parity is even.
JS symbol bit is & quot; 1"
3 & gt; Loop control command (short transfer)
loop CX is not zero.
loop / loopz CX is not zero and flag z = 1.
loop Ne / loopnz CX is not zero and flag z = 0.
jcxz CX is zero.
jecxz ECX is zero.
4 & gt; Interrupt instruction
int interrupt instruction
into overflow interrupt
IRET interrupt return
5 & gt; Processor control instruction
HLT processor pause, When the chip lead test is high, the CPU will enter the waiting state.
ESC switches to the external processor.
lock blocks the bus.
NOP null operation.
STC set carry flag.
CLC clear carry flag.
CMC carry flag Flag reverse.
STD set direction flag.
CLD clear direction flag.
STI set interrupt permission.
cli clear interrupt permission.
VI Pseudo instruction
DW definition word (2 bytes).
proc definition process.
end process.
segment definition segment.
establish segment register addressing.
ends segment.
end program.
seven bit operation instruction, Processor control instruction
1. Bit operation instruction, a new set of instructions in 8086, including bit test and bit scan. BT, BTC, BTR, BTS, BSF, BSR
1.1 BT (bit test), bit test instruction, instruction format:
BT OPRD1, oprd2, rule: OPRD1 can be a 16 bit or 32-bit general-purpose register or storage unit. Oprd2 must be an 8-bit immediate or a general-purpose register of the same length as OPRD1. If oprd2 is divided by OPRD1, assuming the quotient is stored in div and the remainder is stored in mod, then mod is the bit number to test OPRD1 operands. Its main function is to send the value of the bit to be tested to cf. take a few simple examples:
1.2 BTC (bit test and complexity). The usage and rules of testing and negating are the same as BT, but the functions are different, It not only sends the value of the bit to be tested to CF, but also reverses the bit< br />1.3 BTR(Bit Test And Reset)，
add, ADC, and, BTC, BTR, BTS, cmpxchg, cmpxch8b, Dec, Inc, neg, not, or, SBB, sub, XOR, xadd, xchg
the lock instruction will change the instruction into an atomic instruction only when the target operand is a memory address; If the destination operand is not memory, a UD (undefined opcode) error is generated
in addition, it should be noted that some compilers will legally compile the lock instruction before the instruction mentioned above (for example, lock mov [data], eax), but will also generate UD errors when running the program
digression: when one of the operands of xchg is memory, the lock instruction will be inserted automatically, which makes the required cycle very long.
BTC DeST, SRC
BTR DeST, SRC
BTS DeST, SRC
function: according to the bit number specified by the source operation, test the destination operands. When the instruction is executed, the status of the bit to be tested is copied to the carry flag CF
BT copies the value of one bit in dest specified by SRC to CF. BTC copies the value of a bit in dest specified by SRC to CF, and reverses the bit in dest. BTR copies the value of one bit in dest specified by SRC to CF, and resets the bit in dest. BTS copies the value of one bit in dest specified by SRC to CF, and copies this bit in dest to CF
the destination operands are 16 bit or 32-bit general-purpose registers or memories, the source operands are 16 bit or 32-bit general-purpose registers, and 8-bit immediate. When the source operands are general-purpose registers, they must be of the same type as the destination operands. The source operand SRC gives the bit number of the destination operand in two ways, that is,
· SRC is an 8-bit immediate number, which directly gives the bit number to be operated in binary form
· SRC is a general-purpose register. If dest is a general-purpose register, the binary value in SRC directly gives the bit number to be operated. If dest is a memory operand and Src is a signed integer, the quotient obtained by dividing the value of SRC by the length of DeST is used as the relative offset of DeST, and the remainder is directly used as the bit number to be operated. The effective address of DeST is the sum of the offset address given by DeST and the relative offset of dest
the instructions BT, BTC, BTR and BTS affect the CF flag bit, and other flag bits are undefined.
1. The opcode F0 is a lock (lock bus prefix). It can only be used before add, ADC, and,
BTC, BTR, BTS, cmpxchg, cmpxch8b, Dec, Inc, neg, not, or SBB, sub, XOR,
xadd, xchg. If it is not used before the above instructions, undefined opcode exception will be generated (see page 586, Volume 2 of Intel manual 06)
2. Windows handles this undefined operation code exception and generates the above dialog box for users to choose. They can only choose to close and modify the program
If there are no other errors in the program, just drop f0nop (90h) in the program1 register reference
the reference register should be preceded by a percent sign%, such as "movl% eax,% ebx"<
80386 has the following registers:
1. Eight 32-bit registers% eax%, ebx%, ECX%, EDX%, EDI%, ESI%, EBP%, esp
2. Eight 16 bit registers, which are actually the lower 16 bits of the above eight 32-bit registers:% ax,% BX,% CX,% DX,% Di,% Si,% BP,% sp
3. 8 8-bit registers: ah% Al% BH% BL% ch% Cl% DH% dl. They are actually the upper 8 bits and lower 8 bits of registers% ax,% BX,% CX,% DX
4, 6 segment registers: CS (code),% DS (data),% SS (stack),% es,% FS,% GS
5. Three control registers: CR0, CR2, CR3
6. 6 debug registers: db0%, db1%, DB2%, db3%, DB6%, DB7
7. 2 test registers: TR6,% TR7
8. 8 floating point register stacks: st (0),% st (1),% st (2),% st (3),% st (4),% st (5),% st (6),% st (7)
2 order of operands
the order of operands is from source (left) to destination (right), such as "movl% eax (source),% ebx (destination)"
3 immediate number
to use an immediate number, add a sign $, such as "movl $0x04%, ebx"
or:
para = 0x04
movl $para, %The result of ebx
instruction execution is to load the immediate number 04H into register ebx
4 symbol constant
symbol constant direct reference, such as
value,. Long 0x12a3f2de
movl value,% ebx
the result of instruction execution is to load the constant 0x12a3f2de into register ebx
5 the length of the operands
the length of the operands is represented by B (byte, 8-bit), w (word, 16 bits), l (long, 32-bits), such as "movb% Al,% BL", "movw% ax,% BX", "movl% eax,% ebx" with the symbols added after the instruction
if the length of the operands is not specified, the compiler will set it according to the length of the target operands. For example, the instruction "mov% ax% BX" is equivalent to "movw% ax% BX" because the length of the target operand BX is word. Similarly, the instruction "mov $4% ebx" is equivalent to the instruction "movl $4% ebx" and "push% Al" is equivalent to "push B% Al". For instructions that do not specify the length of the operands, but the compiler cannot guess, the compiler will report an error, such as the instruction "push $4"
to refer to the symbol address, add the symbol $before the symbol, for example, "movl $value,% ebx" is to load the address of the symbol value into the register ebx
6 symbolic extension and zero extension instructions
most at & T assembly instructions for 80386 are the same as Intel format assembly instructions, while symbolic extension instructions and zero extension instructions are the only instructions with different formats. Symbolic extension instructions and zero extension instructions need to specify the length of the source and destination operands, even if they are implied in some instructions
in at & T syntax, the format of sign extension and zero extension instruction is the basic part & quot; movs" And & quot; movz" Corresponding to movsx and movzx in Intel syntax), followed by the length of source and destination operands. Movsbl means MOVs (from) byte (to) long; Movbw means MOVs (from) byte (to) word; Movswl means MOVs (from) word (to) long. The same is true for the movz instruction. For example, the instruction "movsbl% Al,% EDX" means that the contents of the Al register are symbol extended and placed in the EDX register
other Intel format symbol extension instructions are:
CBW -- sign extend byte in% Al to word in% ax< br />cwde -- sign-extend word in %ax to long in %eax < br />cwd -- sign-extend word in %ax to long in %dx:%ax < br />cdq -- sign-extend dword in %eax to quad in %edx:%eax
the corresponding at & T syntax instructions are cbtw, cwtl, cwtd, CLTD
7 call and jump instructions
the call and jump instructions in the segment are & quot; call"，& quot; ret" And & quot; jmp"， The inter segment call and jump instructions are & quot; lcall"，& quot; lret" And & quot; ljmp"
the format of inter segment call and jump instruction is "lcall / LJMP $section, $offset", while the format of inter segment return instruction is "LRET $stack-adjust"
8 prefix
opcode prefix is used in the following cases:
1. String repeat operation instruction (rep, repne)
2. Specify the segment to be operated (CS, DS, SS, ES, FS, GS)
3. Lock the bus
4. Specify the address and operation size (data16, addr16)
in at & T assembly syntax, opcode prefixes are usually placed on a single line, not followed by any operands. For example, for repeated SCAs instruction, its writing method is:
repne
SCAs
the meaning and usage of the above opcode prefix are as follows:
specify the segment prefix to be operated as CS, DS, SS, ES, FS, and GS. In at & T syntax, you only need to follow the section:memory-operand The corresponding segment prefix is specified. For example: lcall% CS: realmode_ Switch
the prefix of operands / address size is "data16" and & quot; addr16"， They are used to specify 16 bit operands / addresses in 32-bit operands / address codes
the bus is prefixed with "lock" to ensure that all interrupts are prohibited ring the execution of the current instruction in a multiprocessor environment. This prefix is only valid for add, ADC, and, BTC, BTR, BTS, cmpxchg, Dec, Inc, neg, not, or, SBB, sub, XOR, xadd, xchg instructions. If the lock prefix is used before other instructions, it will cause an exception
string repeat operation prefix & quot; rep",& quot; repe",& quot; repne" Used to make string operations repeat% ECX times
9 memory reference
the format of indirect memory reference in Intel syntax is:
section: [base + index * scale + display]
and the corresponding form in at & T syntax is:
section:displacement (base, index, scale)
where base and index are arbitrary 32-bit base and index registers. Scale can be 1, 2, 4, 8. If you do not specify a scale value, the default value is 1. Section can specify any segment register as the segment prefix. The default segment register is different in different situations. If you specify a default segment prefix in an instruction, the compiler does not generate this segment prefix code in the object code
here are some examples:
- 4 (% EBP): base =% EBP, displacement = - 4, section is not specified, because base =% EBP, the default section =% SS, index, scale is not specified, then index is 0< br />
foo(,%eax,4)：index=%eax，scale=4，displacement=foo Other domains are not specified. The default section here is% DS
foo (, 1): this expression refers to the value stored in the address pointed by the pointer foo. Note that there is no base and index in this expression, and there is only a comma. This is an abnormal syntax, but it is legal
% GS: foo: this expression refers to the value of the variable foo placed in the% GS section
if the prefix "*" is specified before the operands for call and jump operations, it means an absolute address call / jump, that is to say, the JMP / call instruction specifies an absolute address. If & quot*& quot;， Then the operand is a relative address
if the operand of any instruction is a memory operation, the instruction must specify its operation size (byte, word, long), that is, it must have an instruction suffix (B, W, l).
Dec (decreement) minus 1 instruction
format: Dec OPR / / byte / word
execute operation: (OPR) & lt- Opr-1) / / except for the CF flag, all the other flag bits are affected
Theinstruction subtracts the contents of the operand by one, and then returns the operand. The operands can be register operands or memory operands
For example: 1. Dec self decreasing function1. Dec (I, n)// i,n:integer; N is self decrement
equivalent to I: = i-n
2.deci// i:integer;
is equivalent to I: = I-1
for example: 2. Dec is a decreasing function
I: = 100
dec(i);
If it is Dec (I, 30),then I = 100-30 = 70
{rrrrrrr}
< H2 > extended data: data transfer instruction
this part of instruction includes general data transfer instruction MOV, conditional transfer instruction cmovcc, stack operation instruction
push / push / push / Pop / PopA / POPAD, exchange instruction xchg / xlat / bswap Address or segment descriptor selection sub transfer instructions lea / LDS / LES / LFS / LGS / LSS, etc
note that cmovcc is not a specific instruction, but an instruction cluster, including a large number of instructions, which are used to decide whether to execute the specified transfer operation according to some bit states of EFLAGS register
integer and logic operations instructions
these instructions are used to perform arithmetic and logic operations, including add instruction add / ADC, subtract instruction sub / SBB, add instruction Inc, subtract instruction Dec, compare operation instruction CMP, multiply instruction mul / imul,
division instruction div / IDIV, symbol extension instruction CBW / CWDE / cdqe, decimal adjustment instruction DAA / Das / AAA / AAS Logic operation instruction not / and / or / XOR / test, etc
shift instructions
these instructions are used to move a register or memory operand a specified number of times. It includes logical shift left instruction SHL, logical shift right instruction SHR, arithmetic shift left instruction Sal, arithmetic shift right instruction SAR, cyclic shift left instruction rol, cyclic shift right instruction ror, etc
bit operation instructions
these instructions include bit test instruction BT, bit test and set instruction BTS, bit test and reset instruction BTR, bit test and reverse instruction BTC, bit forward scan instruction BSF, bit backward scan instruction BSR, etc
condition setting instruction
this is not a specific instruction, but an instruction cluster, including about 30 instructions, which is used to set an 8-bit register or memory operand according to some bit states of EFLAGS register. For example, Sete / setne / setge and so on
control transfer instruction
this part includes unconditional transfer instruction JMP, conditional transfer instruction JCC / jcxz, loop instruction loop / loop / loop ne, procere call instruction call, subprocess return instruction RET, interrupt instruction INTN, int3, into, IRET, etc
note that JCC is an instruction cluster, which contains many instructions and is used to decide whether to transfer or not according to some bit states of EFLAGS register; Int n is the soft interrupt instruction, and N can be a number between 0 and 255 to indicate the interrupt vector number
string operation instruction
these instructions are used to operate data strings, including string transfer instruction MOVs, string comparison instruction CMPs, string scanning instruction scans, string loading instruction LODs, string saving instruction STOs. These instructions can selectively use the prefix of Rep / Rep / repz / repne and repnz to operate continuously
I / O instructions
these instructions are used to exchange data with peripheral devices, including port input instructions in / INS and port output instructions out / outs
high level language auxiliary instructions
these instructions provide convenience for high-level language compiler, including the instruction enter to create stack frame and the instruction lead to release stack frame
control and privilege instructions
this part includes NOP, HLT, wait / mwait, ESC, lock, bound, lgdt / sgdt, LIDT / sidt, lldt / sldt
descriptor segment threshold load instruction LSR, descriptor access read instruction LAR, task register operation instruction LTR / str, request privilege level adjustment instruction arpl, task switch flag clear instruction CLTS, control register and debug register data transfer instruction MOV,
cache control instruction invd / wbinvd / invlpg Model related register read and write instruction rdmsr / wrmsr, processor information acquisition instruction CPUID, timestamp read instruction rdtsc, etc
floating point and multimedia instructions
these instructions are used to accelerate the operation of floating-point data, and SIMD and its extended ssex instructions are used to accelerate multimedia data processing. This part of the instruction data is very large, can not be listed one by one, please refer to the Intel manual
These instructions include invest / invvpid / vmcall / vmclear / vmlaunch / vmresume / vmptrld / vmptrst / vmread / vmwrite / vmxoff / vmon, etc Network -- assembly language (machine oriented programming language)
1.
forward scan instruction
BSF (bit
scan
forward)
format: BSF
DST, RSC
function: scan the first bit containing 1 in RSC operands from right to left, and send the first bit containing 1 to DST operands. If RSC = 0, DST value is uncertain
note: DST and RSC can be 16 bit or 32-bit, but the length should be the same. DST can only be a general-purpose register, RSC can not be an immediate number
flag: if RSC is 0, set ZF = 1; Otherwise, clear 0
ZF, and other flag bits are uncertain<
2.
reverse scan instruction
BSR (bit
scan
reverse)
format: BSR
DST, RSC
function: scan the first bit containing 1 in RSC operands from left to right, and send the first bit containing 1 to DST operands
note: the same as BSF
logo: the influence on logo is the same as BSF
bit test instruction
bit test
BT
DST, SRC
- & gt; CF
bit
test
and
set
BTS
DST, SRC
- & gt; CF
bit test and reset (bit
test
and
rest) BTR
DST, SRC
- & gt; CF
to test and reverse (bit
test
and
complex) BTC
DST, SRC
- & gt; CF
note: the target can be 16 or 32-bit register or memory operands, and the source can be 8-bit immediate, register or memory operands. If the source operands are immediate, their values should not exceed the length of the target operands. If it is not an immediate number, its length must be the same as that of the target. The bit offset of the destination operand starts at the rightmost bit and counts from 0.
The function of this sentence is to make the value of DS data. Data is the data segment that you define. Its function is to assign the value of data segment register DS as data, which means that the data segment points to the correct position
data is assigned to ax, which is just a transitional function. In fact, it is to assign the value to DS
data, which refers to the address of data, It should be randomly assigned
assigning ax value to DS is a transitional function
extended data :
language composition
e to the huge assembly instruction system, it is necessary to build an instruction system, which has a large number of instructions, complex format and poor memory. The most difficult problem in instruction is the addressing mode supported by instruction, and its essence is how to obtain the operands in instruction. For the processor, it is how to find the data he needs
But for the assembly language at the bottom of the computer, this addressing method will involve a large number of computing storage formats, which is closely related to the complex storage management mode, so it is difficult to understand. Finally, assembly instruction is also related to how to affect the flag bit, but the processor flag bit is very complex, so it is difficult to master its mechanism
transfer instruction
includes general data transfer instruction MOV, conditional transfer instruction cmovcc, stack operation instruction push / push / push / Pop / PopA / POPAD, exchange instruction xchg / xlat / bswap, address or segment descriptor selection sub transfer instruction lea / LDS / LES / LFS / LGS / LSS, etc
logic operations
these instructions are used to perform arithmetic and logic operations, including addition instruction add / ADC, subtraction instruction sub / SBB, add instruction Inc, subtract instruction Dec
comparison operation instruction CMP, multiplication instruction mul / imul, division instruction div / IDIV, symbol extension instruction CBW / CWDE / cdqe, decimal adjustment instruction DAA / Das / AAA / AAS Logic operation instruction not / and / or / XOR / test, etc
shift instructions
these instructions are used to move a register or memory operand a specified number of times. It includes logical shift left instruction SHL, logical shift right instruction SHR, arithmetic shift left instruction Sal, arithmetic shift right instruction SAR, cyclic shift left instruction rol, cyclic shift right instruction ror, etc
bit operation
these instructions include bit test instruction BT, bit test and set instruction BTS, bit test and reset instruction BTR, bit test and reverse instruction BTC, bit forward scan instruction BSF, bit backward scan instruction BSR, etc
control transfer
this part includes unconditional transfer instruction JMP, conditional transfer instruction JCC / jcxz, loop / loop / loopne, procere call instruction call, subprocess return instruction RET, interrupt instruction INTN, int3, into, IRET, etc
string operation
these instructions are used to operate data strings, including string transfer instruction MOVs, string comparison instruction CMPs, string scan instruction scans, string load instruction LODs, string save instruction STOs. These instructions can selectively use the prefix of Rep / Rep / repz / repne and repnz to operate continuously
I / O
these instructions are used to exchange data with peripheral devices, including port input instruction in / INS and port output instruction out / outs