BTC motherboard test of Huaqing 13 card
Publish: 2021-04-16 06:39:48
1. Pro4 supports crossfire, 4 memory slots. But only 4-phase power supply, if you want to overclock, it is not as good as the 5-phase power supply of BTC. Motherboard this thing is not necessarily new good, on the contrary, the more new the material is shrinking.
2. With b85m HDS, there are three pciex1 slots on BTC, which are not needed for household use.
these are also cost-effective, and it is cheaper to buy basic HDS for household use.
these are also cost-effective, and it is cheaper to buy basic HDS for household use.
3.
It can support Celeron g1840, but it may need to refresh BIOS
4. If I don't know much about this bitfish. If you are wrong, please understand
last year, bitcoin was quite crazy, with the highest price rising to 120000. Many companies began to launch their own mines or coins at this time of storm, and then publicized that they are regional chain technology, when they get to * * to recycle, how much to guarantee the revenue, and so on. Then it starts to issue, so that people can start to buy money, and then it is stipulated that the transaction can be carried out after * * months or * * coins. This is the beginning of "cutting leeks" by backstage people. It's up to you to decide whether this coin is worth that money or not
other currencies, such as bitcoin and Ethernet, can be traded at any time (if someone buys them), even 0.001 can be traded.
last year, bitcoin was quite crazy, with the highest price rising to 120000. Many companies began to launch their own mines or coins at this time of storm, and then publicized that they are regional chain technology, when they get to * * to recycle, how much to guarantee the revenue, and so on. Then it starts to issue, so that people can start to buy money, and then it is stipulated that the transaction can be carried out after * * months or * * coins. This is the beginning of "cutting leeks" by backstage people. It's up to you to decide whether this coin is worth that money or not
other currencies, such as bitcoin and Ethernet, can be traded at any time (if someone buys them), even 0.001 can be traded.
5.
Try the following methods:
advanced in BIOS - chipset configuration - primary graphics adapter, which is changed to PCI Express
the following igpu multi monitor is disabled
6. For Gigabyte f2a88xm-d3h motherboard can overclocking 399 yuan
7. The memory is OK, but is the contact still normal?
8. It's definitely your power problem! The power supply mole is not related to the main board. Don't wrongly treat Huaqing's things. I am Huaqing's! P4v88 + 1g, WD's 80g are not even bad now! Must be part of the power supply
No, try changing the power supply!? Your power supply should be ordinary! There must be no problem with a great wall~
No, try changing the power supply!? Your power supply should be ordinary! There must be no problem with a great wall~
9. A0 does not pass the CPU self-test, and FF is the same
if you dial the memory, because C1
D3 and D5 are meaningless
computer fault detection card manual
quick check of code meaning: Please input two hexadecimal fault code W_ Yi
fault code list of PCI / ISA al-purpose debug card (only applicable to PCI / ISA al-purpose and PCI single use) iz
code award BIOS AMI BIOS Phoenix and tandy3000 BIOS} 3
00 (see special code meaning) the configuration of the system has been displayed; The control tool int19 will be booted and loaded See special code meaning) (see special code meaning) | +
01 processor test 1, processing state verification, if the test fails, the loop is infinite. The test of processor register is about to start, and non maskable interrupt is about to stop. CPU register test in progress or failure. KIX '
02 determine the type of diagnosis (normal or manufactured). If the keyboard buffer contains data, it will fail. Disable non maskable interrupt; Start by delaying. CMOS write / read in progress or out of order. k_/ A
03 clear 8042 keyboard controller and issue test-kbrd command (Aah). Power on delay completed. ROM b10s check component in progress or out of order. Lvk
04 reset 8042 keyboard controller and verify testkbrd. Keyboard controller reset / power on test. The test of programmable interval timer is in progress or fails[
05 if manufacturing tests 1 to 5 are repeated continuously, 8042 control status can be obtained. Soft reset / power on determined; The ROM is about to start. DMA initial preparation is in progress or fails. CT
06 make the chip initial preparation, disable video, parity, DMA chip, and clear DMA chip, all page registers and CMOS shutdown bytes. Make initial preparation of circuit chip, disable video, parity, DMA circuit chip, and clear DMA circuit chip, all page registers and CMOS shutdown bytes. ROM is started to calculate the sum of ROM BIOS checks and to check if the keyboard buffer is cleared. DMA initial page register read / write test in progress or failure. V9 *
07 processor test 2 to verify the operation of CPU registers. ROM BIOS check sum is normal, keyboard buffer has been cleared, and bat (basic guarantee test) command is issued to keyboard. Meaningless uwfc & gt$
08 enables the CMOS timer to make initial preparation and update the timer cycle normally. Bat command has been issued to the keyboard and will be written. Ram update check in progress or out of order. c' 2 ^
09 EPROM check sum and must be equal to zero before passing. Verify the basic guarantee test of the keyboard, and then verify the keyboard command byte. The first 64K ram test is in progress@
0A makes the initial preparation for the video interface. Issue the keyboard command byte code, and write the command byte data. The first 64K RAM chip or data line failed and shifted. Am? CV $
0b tests 8254 channel 0. Write the command byte of keyboard controller, and the lock / unlock command of pins 23 and 24 will be issued. The first 64K ram odd / even logic fails. A | ys
0C tests 8054 channel 1. Keyboard controller pins 23 and 24 are locked / unlocked; NOP command issued. The address line of the first 64K ram is faulty. Jixy'
0d 1. Check whether the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip meets the initial setting. 3. Video channel test, if failed, honk the horn. NOP command has been processed; Then test the CMOS stop register. Parity failure of the first 64K ram; U;
0e test CMOS shutdown byte. CMOS stop register read / write test; The CMOS check sum is calculated. Initial cargo I / O port address. EJ IB
0f test extended CMOS. The sum of CMOS check has been calculated and written into the diagnostic byte; CMOS starts initial preparation. meaningless. N
10 test DMA channel 0. The CMOS has been initially prepared, and the CMOS status register is about to be initially prepared for the date and time. The first 64K ram bit 0 is faulty. Vl2nj
11 tests DMA channel 1. COMS status register is ready to disable DMA and interrupt controller. The first 64K ram bit 1 is faulty. VG * l:%
12 test DMA page register. Disable DMA controller 1 and interrupt controllers 1 and 2; The video display will be ready and port B will be ready. The first 64K ram bit 2 is faulty. Q'
13 test 8471 keyboard controller interface. The video display has been disabled and port B has made initial preparation; Chip initialization / memory auto detection is about to start. The first 64K ram bit 3 is faulty
14 test memory update trigger circuit. The chip initialization / memory auto detection is finished; 8254 timer test is about to begin. The first 64K ram bit 4 is faulty. E_ J
15 test the first 64K system memory. Half of the second channel timer is tested; 8254 channel 2 timer is about to finish testing. The first 64K ram bit 5 is faulty*= WG
16 creates the interrupt vector table for 8259. The second channel timer test is finished; 8254 channel 1 timer is about to finish testing. The first 64K ram bit 6 is faulty, E4 ^ o
17 adjust the video input / output, and enable it if the video BIOS is installed. The first channel timer test is finished; 8254 channel 0 is about to be tested. The first 64K ram bit 7 is faulty. Kw0 /
18 test video memory, if the installation of the selected video BIOS passed, it can be bypassed. The timer test of channel 0 is finished; The memory update is about to start. Bit 8 of the first 64K ram is faulty. OPH
19 test the interrupt controller (8259) mask bit of channel 1. The update of the memory has started, and then the update of the memory will be completed. The first 64K ram bit 9 is faulty.] '} G * e
1A test the shielding bit of interrupt controller (8259) of channel 2. Triggering memory update line, about to check 15 microseconds on / off time. The first 64K ram bit 10 is faulty&# 39;& quot; Xvgr
1b mode CMOS battery level. Complete the memory update time 30 microseconds test; The basic 64K memory test is about to start. Bit 11 of the first 64K ram is faulty= 7igyt
1C test COMS check sum. meaningless. The first 64K ram bit 12 is faulty. R
1D to set COMS configuration. meaningless. Bit 13 of the first 64K ram is faulty_
1E measure the size of system memory, and compare the objective existence with COMS value. meaningless. Bit 14 of the first 64K ram is faulty=
1F tests 64K memory to a maximum of 640K. meaningless. The first 64K ram bit 15 is faulty& quot; No
20 was measured in fixed 8259. Start basic 64K memory test; The address line is about to be tested. Slave DMA register test in progress or failed. 3 ^ sh
21 maintain non maskable interrupt (NMI) bit (parity or I / O channel check). Pass the address line test; Parity is about to be triggered. Master DMA register test in progress or failed. 8zg # g
22 tests the interrupt function of 8259. End trigger parity; The serial data read / write test will begin. The master interrupt mask register is in progress or out of order. Vm'(
23 test protection mode: 8086 virtual mode and 8186 page mode. The basic 64K serial data read / write test is normal; Any adjustment before interrupt vector initialization is about to start. Slave interrupt mask register test in progress or failed. L {ug4
24} was used to measure the extended memory of more than 1MB. When any adjustment before vector initialization is completed, the initial preparation of interrupt vector will begin. Set the ES segment address register to the high end of memory. JXU
25 tests all memories except the first 64K. Complete the initial preparation of interrupt vector; The I / O port of 8042 will be read out for rotation arbitrary. Load interrupt vector in progress or out of order. X2i
26 test the exception of protection mode. Read and write the input / output port of 8042; We are about to start the initial preparation of global data for rotary intermittent. Turn on A20 address line; Make it participate in addressing. 2L -
27 determines the control or masking ram of the cache. All 1 data initial preparation is completed; Any initial preparation after the interrupt vector is then performed. Keyboard controller test in progress or out of order& quot;` Kn
28 determines the control of the cache or the special 8042 keyboard controller. Finish the initial preparation after interrupt vector; It is about to set the monochrome wide style. CMOS power failure / check summation calculation in progress. (? Wnpd
29 had no significance. Monochrome mode has been set, color mode will be set soon. The check of CMOS configuration validity is in progress. 7
2A makes the keyboard controller make initial preparation. The color mode has been set to trigger parity before ROM test. Empty 64K basic memory. S2" F
2B makes the disk drive and controller initially ready. Trigger the end of parity; About to control any adjustments required before checking the optional video ROM. Screen memory test in progress or out of order. 73 = 2
2C check the serial port and make initial preparation. Complete the processing before video ROM control; About to view and control the optional video ROM. Screen initial preparation in progress or out of order. tArEg'
2D checks the parallel serial port and makes initial preparation. To complete the optional video ROM control, that is, to control any other processing after the video ROM recovery control. Screen flyback test in progress or out of order+&# 92; Kqx
2E makes the disk drive and controller initially ready. Recover the processing after controlling the video ROM; If EGA / VGA is not found, read and write test of display memory should be carried out. Check video ROM in progress. D {I
2F detects the math coprocessor and makes it do initial preparation. No EGA / VGA was found; The display memory read / write test is about to start. meaningless. DPSA -
30 establishes basic memory and extended memory. Read / write test of display memory; The scan will be carried out soon. I think the screen works. Ad $(f
31) was used to detect the ROM from c800:0 to efff:0 and prepare it for life. Display memory read / write test failed, another display memory read / write test will be performed soon. Monochrome monitors work. G
32 program the I / O chips such as COM / LTP / FDD / sound devices on the motherboard to suit the setting value. Through another display memory read / write test; Another monitor scan is about to be performed. The color monitor (40 columns) works. Z2%
33 had no significance. The video display inspection is finished; You will begin to verify the type of display using the adjustment switch and the actual card. The color monitor (80 columns) works. N ~ 9z ~ C
34 had no significance. The display adapter has been verified; Next, the display mode will be set. Timer tick interrupt test in progress or out of order. U) ^ hot
35 is meaningless. Finish setting display mode; You are about to check the data area of the BIOS ROM. Shutdown detection in progress or out of order&# 92;
36 is meaningless. The BIOS ROM data area has been checked; The cursor that is about to set the power on information. A-20 in the gate circuit is out of order. H # ^ IVF
37 had no significance. The vernier setting for identifying the power on information has been completed; The power on message will be displayed. Unexpected interruption in protection mode. h;? B
38 had no significance. Complete the display of power on information; The new cursor position will be read out. Ram test in progress or address failure&
if you dial the memory, because C1
D3 and D5 are meaningless
computer fault detection card manual
quick check of code meaning: Please input two hexadecimal fault code W_ Yi
fault code list of PCI / ISA al-purpose debug card (only applicable to PCI / ISA al-purpose and PCI single use) iz
code award BIOS AMI BIOS Phoenix and tandy3000 BIOS} 3
00 (see special code meaning) the configuration of the system has been displayed; The control tool int19 will be booted and loaded See special code meaning) (see special code meaning) | +
01 processor test 1, processing state verification, if the test fails, the loop is infinite. The test of processor register is about to start, and non maskable interrupt is about to stop. CPU register test in progress or failure. KIX '
02 determine the type of diagnosis (normal or manufactured). If the keyboard buffer contains data, it will fail. Disable non maskable interrupt; Start by delaying. CMOS write / read in progress or out of order. k_/ A
03 clear 8042 keyboard controller and issue test-kbrd command (Aah). Power on delay completed. ROM b10s check component in progress or out of order. Lvk
04 reset 8042 keyboard controller and verify testkbrd. Keyboard controller reset / power on test. The test of programmable interval timer is in progress or fails[
05 if manufacturing tests 1 to 5 are repeated continuously, 8042 control status can be obtained. Soft reset / power on determined; The ROM is about to start. DMA initial preparation is in progress or fails. CT
06 make the chip initial preparation, disable video, parity, DMA chip, and clear DMA chip, all page registers and CMOS shutdown bytes. Make initial preparation of circuit chip, disable video, parity, DMA circuit chip, and clear DMA circuit chip, all page registers and CMOS shutdown bytes. ROM is started to calculate the sum of ROM BIOS checks and to check if the keyboard buffer is cleared. DMA initial page register read / write test in progress or failure. V9 *
07 processor test 2 to verify the operation of CPU registers. ROM BIOS check sum is normal, keyboard buffer has been cleared, and bat (basic guarantee test) command is issued to keyboard. Meaningless uwfc & gt$
08 enables the CMOS timer to make initial preparation and update the timer cycle normally. Bat command has been issued to the keyboard and will be written. Ram update check in progress or out of order. c' 2 ^
09 EPROM check sum and must be equal to zero before passing. Verify the basic guarantee test of the keyboard, and then verify the keyboard command byte. The first 64K ram test is in progress@
0A makes the initial preparation for the video interface. Issue the keyboard command byte code, and write the command byte data. The first 64K RAM chip or data line failed and shifted. Am? CV $
0b tests 8254 channel 0. Write the command byte of keyboard controller, and the lock / unlock command of pins 23 and 24 will be issued. The first 64K ram odd / even logic fails. A | ys
0C tests 8054 channel 1. Keyboard controller pins 23 and 24 are locked / unlocked; NOP command issued. The address line of the first 64K ram is faulty. Jixy'
0d 1. Check whether the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip meets the initial setting. 3. Video channel test, if failed, honk the horn. NOP command has been processed; Then test the CMOS stop register. Parity failure of the first 64K ram; U;
0e test CMOS shutdown byte. CMOS stop register read / write test; The CMOS check sum is calculated. Initial cargo I / O port address. EJ IB
0f test extended CMOS. The sum of CMOS check has been calculated and written into the diagnostic byte; CMOS starts initial preparation. meaningless. N
10 test DMA channel 0. The CMOS has been initially prepared, and the CMOS status register is about to be initially prepared for the date and time. The first 64K ram bit 0 is faulty. Vl2nj
11 tests DMA channel 1. COMS status register is ready to disable DMA and interrupt controller. The first 64K ram bit 1 is faulty. VG * l:%
12 test DMA page register. Disable DMA controller 1 and interrupt controllers 1 and 2; The video display will be ready and port B will be ready. The first 64K ram bit 2 is faulty. Q'
13 test 8471 keyboard controller interface. The video display has been disabled and port B has made initial preparation; Chip initialization / memory auto detection is about to start. The first 64K ram bit 3 is faulty
14 test memory update trigger circuit. The chip initialization / memory auto detection is finished; 8254 timer test is about to begin. The first 64K ram bit 4 is faulty. E_ J
15 test the first 64K system memory. Half of the second channel timer is tested; 8254 channel 2 timer is about to finish testing. The first 64K ram bit 5 is faulty*= WG
16 creates the interrupt vector table for 8259. The second channel timer test is finished; 8254 channel 1 timer is about to finish testing. The first 64K ram bit 6 is faulty, E4 ^ o
17 adjust the video input / output, and enable it if the video BIOS is installed. The first channel timer test is finished; 8254 channel 0 is about to be tested. The first 64K ram bit 7 is faulty. Kw0 /
18 test video memory, if the installation of the selected video BIOS passed, it can be bypassed. The timer test of channel 0 is finished; The memory update is about to start. Bit 8 of the first 64K ram is faulty. OPH
19 test the interrupt controller (8259) mask bit of channel 1. The update of the memory has started, and then the update of the memory will be completed. The first 64K ram bit 9 is faulty.] '} G * e
1A test the shielding bit of interrupt controller (8259) of channel 2. Triggering memory update line, about to check 15 microseconds on / off time. The first 64K ram bit 10 is faulty&# 39;& quot; Xvgr
1b mode CMOS battery level. Complete the memory update time 30 microseconds test; The basic 64K memory test is about to start. Bit 11 of the first 64K ram is faulty= 7igyt
1C test COMS check sum. meaningless. The first 64K ram bit 12 is faulty. R
1D to set COMS configuration. meaningless. Bit 13 of the first 64K ram is faulty_
1E measure the size of system memory, and compare the objective existence with COMS value. meaningless. Bit 14 of the first 64K ram is faulty=
1F tests 64K memory to a maximum of 640K. meaningless. The first 64K ram bit 15 is faulty& quot; No
20 was measured in fixed 8259. Start basic 64K memory test; The address line is about to be tested. Slave DMA register test in progress or failed. 3 ^ sh
21 maintain non maskable interrupt (NMI) bit (parity or I / O channel check). Pass the address line test; Parity is about to be triggered. Master DMA register test in progress or failed. 8zg # g
22 tests the interrupt function of 8259. End trigger parity; The serial data read / write test will begin. The master interrupt mask register is in progress or out of order. Vm'(
23 test protection mode: 8086 virtual mode and 8186 page mode. The basic 64K serial data read / write test is normal; Any adjustment before interrupt vector initialization is about to start. Slave interrupt mask register test in progress or failed. L {ug4
24} was used to measure the extended memory of more than 1MB. When any adjustment before vector initialization is completed, the initial preparation of interrupt vector will begin. Set the ES segment address register to the high end of memory. JXU
25 tests all memories except the first 64K. Complete the initial preparation of interrupt vector; The I / O port of 8042 will be read out for rotation arbitrary. Load interrupt vector in progress or out of order. X2i
26 test the exception of protection mode. Read and write the input / output port of 8042; We are about to start the initial preparation of global data for rotary intermittent. Turn on A20 address line; Make it participate in addressing. 2L -
27 determines the control or masking ram of the cache. All 1 data initial preparation is completed; Any initial preparation after the interrupt vector is then performed. Keyboard controller test in progress or out of order& quot;` Kn
28 determines the control of the cache or the special 8042 keyboard controller. Finish the initial preparation after interrupt vector; It is about to set the monochrome wide style. CMOS power failure / check summation calculation in progress. (? Wnpd
29 had no significance. Monochrome mode has been set, color mode will be set soon. The check of CMOS configuration validity is in progress. 7
2A makes the keyboard controller make initial preparation. The color mode has been set to trigger parity before ROM test. Empty 64K basic memory. S2" F
2B makes the disk drive and controller initially ready. Trigger the end of parity; About to control any adjustments required before checking the optional video ROM. Screen memory test in progress or out of order. 73 = 2
2C check the serial port and make initial preparation. Complete the processing before video ROM control; About to view and control the optional video ROM. Screen initial preparation in progress or out of order. tArEg'
2D checks the parallel serial port and makes initial preparation. To complete the optional video ROM control, that is, to control any other processing after the video ROM recovery control. Screen flyback test in progress or out of order+&# 92; Kqx
2E makes the disk drive and controller initially ready. Recover the processing after controlling the video ROM; If EGA / VGA is not found, read and write test of display memory should be carried out. Check video ROM in progress. D {I
2F detects the math coprocessor and makes it do initial preparation. No EGA / VGA was found; The display memory read / write test is about to start. meaningless. DPSA -
30 establishes basic memory and extended memory. Read / write test of display memory; The scan will be carried out soon. I think the screen works. Ad $(f
31) was used to detect the ROM from c800:0 to efff:0 and prepare it for life. Display memory read / write test failed, another display memory read / write test will be performed soon. Monochrome monitors work. G
32 program the I / O chips such as COM / LTP / FDD / sound devices on the motherboard to suit the setting value. Through another display memory read / write test; Another monitor scan is about to be performed. The color monitor (40 columns) works. Z2%
33 had no significance. The video display inspection is finished; You will begin to verify the type of display using the adjustment switch and the actual card. The color monitor (80 columns) works. N ~ 9z ~ C
34 had no significance. The display adapter has been verified; Next, the display mode will be set. Timer tick interrupt test in progress or out of order. U) ^ hot
35 is meaningless. Finish setting display mode; You are about to check the data area of the BIOS ROM. Shutdown detection in progress or out of order&# 92;
36 is meaningless. The BIOS ROM data area has been checked; The cursor that is about to set the power on information. A-20 in the gate circuit is out of order. H # ^ IVF
37 had no significance. The vernier setting for identifying the power on information has been completed; The power on message will be displayed. Unexpected interruption in protection mode. h;? B
38 had no significance. Complete the display of power on information; The new cursor position will be read out. Ram test in progress or address failure&
10. 1. BIOS settings are generally the first major item. There is a boot error detection, which is usually set as all error. You can change it to no error, and the boot will not be interrupted when the error is detected.
2, This is caused by improper BIOS settings on the motherboard. You can press del key to enter BIOS setting before starting the machine, then select "standards BIOS Setup", find the "quick test" setting item, set its value to enabled, save the setting and exit. In this way, the memory will be detected only once when starting the self-test
3. For disk self checking:
right click the disk (such as disk C, it is better to repair every disk), then click the "tools" tab under the "properties" command, and then click the "start checking" button to check before "automatically repair file system errors" and "scan and try to recover bad sectors". Finally, click the start button. After the repair, generally do not carry out the disk self-test next time
or. Permanently cancel a disk self-test:
just input in "start" - "run": (take Disk C as an example)
chkntfs / T: 0
chkntfs / X C: 0
2, This is caused by improper BIOS settings on the motherboard. You can press del key to enter BIOS setting before starting the machine, then select "standards BIOS Setup", find the "quick test" setting item, set its value to enabled, save the setting and exit. In this way, the memory will be detected only once when starting the self-test
3. For disk self checking:
right click the disk (such as disk C, it is better to repair every disk), then click the "tools" tab under the "properties" command, and then click the "start checking" button to check before "automatically repair file system errors" and "scan and try to recover bad sectors". Finally, click the start button. After the repair, generally do not carry out the disk self-test next time
or. Permanently cancel a disk self-test:
just input in "start" - "run": (take Disk C as an example)
chkntfs / T: 0
chkntfs / X C: 0
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