How can Shiqiao get to nanfenghui global exhibition and Trade Ce
Publish: 2021-05-08 17:26:21
1. I am currently studying in California, and I am quite familiar with it.
Beverly Hills refers to a very high-end city in California, where many stars live. Of course, a city in California is not the same as a big district in Beijing.
Beverly Hills plastic surgery refers to the well-known plastic surgery technology in that area, because many stars are in plastic surgery, not just any hospital
Beverly Hills refers to a very high-end city in California, where many stars live. Of course, a city in California is not the same as a big district in Beijing.
Beverly Hills plastic surgery refers to the well-known plastic surgery technology in that area, because many stars are in plastic surgery, not just any hospital
2. Unknown_Error
3. Because the new version of CentOS uses SYSTEMd, which is a system and service manager. It will automatically name the device. Under the management of SYSTEMd, the previous eth0 will become a strange eno followed by a series of random numbers. In an instant, the knowledge in the textbook becomes the knowledge of the last century. What should we do? Just name it eth0. Edit the content of / etc / sysconfig / grub file, add "net. Ifnames = 0, biosdevname = 0", execute: Grub2 mkconfig - O / boot / Grub2 / grub. CFG, rename the file
MV / etc / sysconfig / network scripts / ifcfg ENS & #; X' X' X' / Etc / sysconfig / network scripts / ifcfg-eth0
pay attention to the & 39; X' X' X' It's a random number after your network card. Each machine is different. Eth0 is the name of the network card device after you rename it
then edit the file / etc / sysconfig / network scripts / ifcfg-eth0, name = ENS & # 39; X' X' X' Change to name = eth0. Save, exit and restart the server.
MV / etc / sysconfig / network scripts / ifcfg ENS & #; X' X' X' / Etc / sysconfig / network scripts / ifcfg-eth0
pay attention to the & 39; X' X' X' It's a random number after your network card. Each machine is different. Eth0 is the name of the network card device after you rename it
then edit the file / etc / sysconfig / network scripts / ifcfg-eth0, name = ENS & # 39; X' X' X' Change to name = eth0. Save, exit and restart the server.
4. The network card of centos7 is no longer eth0 by default
eth0 is an old system
now it usually starts with em or ENS
you can see it in the directory of network card
in addition, the IP command
ifconfig is used to check the network card of the new system, and you can display the network card information without
IP a
eth0 is an old system
now it usually starts with em or ENS
you can see it in the directory of network card
in addition, the IP command
ifconfig is used to check the network card of the new system, and you can display the network card information without
IP a
5. I teach you, one is to search in the mine cave, the other is to use the creation of the same map seed to search for the mine, and then record the coordinates, and dig when the survival or limit reaches the coordinates
6. You can see that in addition to the IO you use, there are many sysrq / tr. SCI / IIC IO, it is these IO to build a channel to communicate with the computer< There are several ways to make the emulator transparent:
1. Use the MCU directly on the emulator, plug it into the socket directly, and use PC software to interrupt and monitor the function of the MCU. This is more real, but it takes up some internal resources of the MCU
2. The MCU chip specially designed by the MCU manufacturer is actually a al core MCU, and the manufacturer has a deep understanding. This method can completely transparently simulate MCU, such as some emulators of Philips or microchip, but it is generally more expensive
3. The al MCU mode developed by some people can also be as transparent as possible
4. Complete software simulation, shown in hardware, is actually indirect call
5. Some internal MCU with ICP or ISP function have two parts of memory, one part calls the other part to achieve the purpose of simulation
they have something in common with my answer.
1. Use the MCU directly on the emulator, plug it into the socket directly, and use PC software to interrupt and monitor the function of the MCU. This is more real, but it takes up some internal resources of the MCU
2. The MCU chip specially designed by the MCU manufacturer is actually a al core MCU, and the manufacturer has a deep understanding. This method can completely transparently simulate MCU, such as some emulators of Philips or microchip, but it is generally more expensive
3. The al MCU mode developed by some people can also be as transparent as possible
4. Complete software simulation, shown in hardware, is actually indirect call
5. Some internal MCU with ICP or ISP function have two parts of memory, one part calls the other part to achieve the purpose of simulation
they have something in common with my answer.
7. Delay read, read twice for each port. In addition,
decoupling capacitor is added to the external IO pin.
decoupling capacitor is added to the external IO pin.
8. MCS-51 single chip microcomputer series
divided by process:
> HMOs process procts: such as 8031, 8051, 8751, etc< HCMOS process procts: such as 80C31, 80C51, 87C51, etc; According to the types of ROM:
> ROM procts,
> Prom procts, 8051
> EPROM procts, 87C51, 87c52
> flash procts: AT89C51, AT89C52
(2) the internal structure of MCS-51 microcontroller Arithmetic unit: PSW consists of ALU, ACC, B register, two temporary registers and program status register; 8 bits, which can carry out arithmetic cloud computing (addition, subtraction, multiplication, division, multiplication and division related to register b), logic operation and shift operation, etc< 2. Controller: it is composed of instruction register IR, instruction decoder ID, timing and control logic circuit, and program counter PC, which is the operation control center of MCU
PC structure and function: 16 bit program register to control the execution of the program
IR, ID function< Second, 8051 chip memory
ROM: 4KB, address 0000H -- 0fffh (when used)
> ram: 128B, address 00h -- 7FH
Third, 8051 I / O port circuit
Fourth, timer / counter: Two 16 bit timers / counters
fifth, interrupt control system: five interrupt sources, There are two external interrupts, two timer / counter interrupts and one serial port interrupt< 6. Serial port: a fully functional asynchronous serial port 7. Clock circuit: a complete oscillation circuit can be formed by adding crystal oscillator and capacitor outside the clock circuit to provide clock for the system< Bus: connecting all parts of the system into an organic whole through the internal bus< (3) signal pin of MCS-51 single chip microcomputer:
I. pin introction:
input / output port line:
> port P0: Address / data multiplexing port
> port P2: high 8-bit address port
> port P1: general I / O port
> port P3: general I / O port The second function port (serial port)
port and port line representation method: P0, P1, P2, P3; P1.0, P1.1
ale: address latch control signal, used for synchronous control of external memory or I / O port bus access, so as to make the address / data signal flow orderly on the bus
PSEN: read gate signal of external program memory. When PSEN signal is low, it means to access external program memory
RST: system reset signal. The high level (more than two clock cycles) on this pin will make the system enter the reset state<
xtal1, xtal2: external crystal pin
VSS, VCC: ground Power supply
2. Second function of signal pin
1). Second function of P3 port
RXD (P3.0): serial data receiving terminal
TXD (P3.1): serial data sending terminal
/ INT0 (p3.2): external interrupt 0 application signal input terminal
/ INT1 (p3.3): external interrupt 1 application signal input terminal
t0 (p3.4): timer / meter Counter 0 count input terminal
T1 (p3.5): timer / counter 1 count input terminal
/ WR (P3.6): external RAM write gate
/ RD (P3.7): external RAM read gate
/ prog (ALE): programming pulse input terminal
VPP (/ EA): programming voltage input terminal
VPD (RST): standby power input terminal
3. Single chip microcomputer Three bus structure:
address bus: P0: A0 ~ A7, P2: A8 ~ A15
data bus: P0: d0 ~ D7
control bus: WR, / RD, / PSEN, ale, / EA
(IV) clock and timing of MCS-51 single chip microcomputer
(1), internal clock mode:
(2), and External clock mode: xtal1-gnd, xtal2-external clock signal
2. Timing signal:
> crystal period: t0
> State Period: 2t0
> machine period: 12t0
> instruction period: at least 12t0
. 3. 8051 finger taking and instruction execution
(1) Single cycle instruction
(2), double cycle instruction
(3), multi cycle instruction
section 2 internal memory of MCS-51 MCU
requirements: master the mechanism and use of internal data memory of MCS-51 MCU, master the basic method of stack operation, and master the allocation and use of program memory
an internal RAM low 128 byte unit: Address: 00h ~ 7FH
1. General register area: (address: 00h ~ 1fh)
divided into four groups: group 0: 00h ~ 07h
group 1: 08h ~ 0Fh
group 2: 10h ~ 17h
group 3: 18h ~ 1fh
current register group: RS1 of PSW register The combination of rs0 determines the access modes supported by
including register addressing, direct addressing and inter address addressing, 128 bit units)
arrangement of bit address: 00h ~ 7FH
access of bit address space: access by byte mode
access by bit addressing mode
3. RAM area: (address range: 30h ~ 7FH, a total of 80 units)
the space can be freely arranged by users, It is mainly used for stack development and user variable storage< The special function registers of MCS-51 single chip microcomputer are allocated to the high 128 byte unit of internal RAM. There are 22 special function registers in total, of which 21 can be accessed. Except the units occupied by registers, the remaining units can no longer be used by users, Instead, it is reserved by the system and used in later extended design<
Introction to main SFR:
program pointer register PC (program counter)
16 bit, accessible program memory space 64K, the user can not directly modify the value of the register with instructions, but the execution of transfer, call, return and other instructions can cause the change of PC value
accumulator A:
ACC is the main place of arithmetic and logic operation, the storage place of operation results, the transfer station of data transmission, and can also be used for index addressing. The frequency of use of this register is very high, and its use is very important
register B: mainly used with ACC to complete multiplication and division< PSW (program status word):
CY
AC
F0
RS1
rs0
ov
/
P
Cy: carry or borrow flag bit
AC: auxiliary carry flag bit
F0: user flag bit
rs1rs0: general register group selection bit
ov: overflow flag bit Log bit
P: parity flag bit
data pointer dptr: 16 bit data pointer, which can be divided into two 8-bit registers (DPL, DPH), mainly used to access the address register of the external data space and the table access of the program memory<
addressing problem of special function registers:
SFR can only use direct addressing mode by byte access. Specific usage examples are as follows:
mov P0, # 55h
mov 80h, # 55h
the functions and instruction codes of these two instructions are exactly the same, That is to say, the special function register can be accessed by the name or address of the register. Here 80h is the register address of port P0
bit access of special registers: there are 11 special registers that can be accessed bit by bit. The corresponding bits of these special function registers have corresponding bit addresses. Examples of accessing these bits are as follows:
CLR 80h
CLR p0.0
the functions of these two instructions are the same, but the representation methods are different, That is to say, the specific bit can be accessed by the bit address of the corresponding bit or by the name of the bit, while other bits in the register are not affected
3 The stack and its operation of MCS-51
the main function of the stack is to protect breakpoints and program sites
save user data
operation rules of the stack: first in, last out
specific operation of the stack:
creation of the stack: usually the stack pointer points to the user's RAM area ring initialization
operation of the stack: push direct_ address SP+1 → SP,(direct_ Address) → stack top unit
stack exit operation: pop direct_ addree The content of the top unit of the stack → (direct)_ 4. The allocation and use of ROM space of MCS-51 single chip microcomputer
> 0000H -- 0002h: program entry address
> 0003h -- 000ah: INT0 entry address< 000BH -- 0012h: timer0 interrupt entry address<
> 0013h -- 001ah: INT1 entry address:
> 001bh -- 0022h: Timer1 interrupt entry address< 0023h -- 002ah: serial port interrupt entry address< 002bh-ffffh: allocated by users< Summary:
ROM space:
> internal 4KB (0000H -- 0fffh) + external 60kb (1000h-ffffh) = 64KB (EA = 1)< External 64KB (0000h-ffffh) (EA = 0)<
RAM space:
> internal RAM: 00h-ffh (independent)< External RAM: 0000h-ffffh (independent of internal RAM)< Requirements: be familiar with the structure of MCS-51 parallel port and master the main functions of each parallel port< (1) port P0 is used as I / O port: MOV instruction, MUX to / Q, T1 stop
(1) port P0 is used as output: output latch, OC gate output
(2) port P0 is used as input: the read in state is not necessarily the same as the current register state, To input the status of the external pin, write high level to the corresponding pin first, and turn off T2< (2) port P0 is used as address / data bus: MOVC and MOVX instructions, MUX calls to a / D line
]. Port P0 is used as bus read: output address lower 8 bits first, then output data
]. Port P0 is used as bus write: output address lower 8 bits first, then input data
(2) structure of port P2
(1) P2 is used as a general-purpose I / O port
C = 0, MUX is connected with Q
output is pulled up internally and output is locked< (2) P2 port
divided by process:
> HMOs process procts: such as 8031, 8051, 8751, etc< HCMOS process procts: such as 80C31, 80C51, 87C51, etc; According to the types of ROM:
> ROM procts,
> Prom procts, 8051
> EPROM procts, 87C51, 87c52
> flash procts: AT89C51, AT89C52
(2) the internal structure of MCS-51 microcontroller Arithmetic unit: PSW consists of ALU, ACC, B register, two temporary registers and program status register; 8 bits, which can carry out arithmetic cloud computing (addition, subtraction, multiplication, division, multiplication and division related to register b), logic operation and shift operation, etc< 2. Controller: it is composed of instruction register IR, instruction decoder ID, timing and control logic circuit, and program counter PC, which is the operation control center of MCU
PC structure and function: 16 bit program register to control the execution of the program
IR, ID function< Second, 8051 chip memory
ROM: 4KB, address 0000H -- 0fffh (when used)
> ram: 128B, address 00h -- 7FH
Third, 8051 I / O port circuit
Fourth, timer / counter: Two 16 bit timers / counters
fifth, interrupt control system: five interrupt sources, There are two external interrupts, two timer / counter interrupts and one serial port interrupt< 6. Serial port: a fully functional asynchronous serial port 7. Clock circuit: a complete oscillation circuit can be formed by adding crystal oscillator and capacitor outside the clock circuit to provide clock for the system< Bus: connecting all parts of the system into an organic whole through the internal bus< (3) signal pin of MCS-51 single chip microcomputer:
I. pin introction:
input / output port line:
> port P0: Address / data multiplexing port
> port P2: high 8-bit address port
> port P1: general I / O port
> port P3: general I / O port The second function port (serial port)
port and port line representation method: P0, P1, P2, P3; P1.0, P1.1
ale: address latch control signal, used for synchronous control of external memory or I / O port bus access, so as to make the address / data signal flow orderly on the bus
PSEN: read gate signal of external program memory. When PSEN signal is low, it means to access external program memory
RST: system reset signal. The high level (more than two clock cycles) on this pin will make the system enter the reset state<
xtal1, xtal2: external crystal pin
VSS, VCC: ground Power supply
2. Second function of signal pin
1). Second function of P3 port
RXD (P3.0): serial data receiving terminal
TXD (P3.1): serial data sending terminal
/ INT0 (p3.2): external interrupt 0 application signal input terminal
/ INT1 (p3.3): external interrupt 1 application signal input terminal
t0 (p3.4): timer / meter Counter 0 count input terminal
T1 (p3.5): timer / counter 1 count input terminal
/ WR (P3.6): external RAM write gate
/ RD (P3.7): external RAM read gate
/ prog (ALE): programming pulse input terminal
VPP (/ EA): programming voltage input terminal
VPD (RST): standby power input terminal
3. Single chip microcomputer Three bus structure:
address bus: P0: A0 ~ A7, P2: A8 ~ A15
data bus: P0: d0 ~ D7
control bus: WR, / RD, / PSEN, ale, / EA
(IV) clock and timing of MCS-51 single chip microcomputer
(1), internal clock mode:
(2), and External clock mode: xtal1-gnd, xtal2-external clock signal
2. Timing signal:
> crystal period: t0
> State Period: 2t0
> machine period: 12t0
> instruction period: at least 12t0
. 3. 8051 finger taking and instruction execution
(1) Single cycle instruction
(2), double cycle instruction
(3), multi cycle instruction
section 2 internal memory of MCS-51 MCU
requirements: master the mechanism and use of internal data memory of MCS-51 MCU, master the basic method of stack operation, and master the allocation and use of program memory
an internal RAM low 128 byte unit: Address: 00h ~ 7FH
1. General register area: (address: 00h ~ 1fh)
divided into four groups: group 0: 00h ~ 07h
group 1: 08h ~ 0Fh
group 2: 10h ~ 17h
group 3: 18h ~ 1fh
current register group: RS1 of PSW register The combination of rs0 determines the access modes supported by
including register addressing, direct addressing and inter address addressing, 128 bit units)
arrangement of bit address: 00h ~ 7FH
access of bit address space: access by byte mode
access by bit addressing mode
3. RAM area: (address range: 30h ~ 7FH, a total of 80 units)
the space can be freely arranged by users, It is mainly used for stack development and user variable storage< The special function registers of MCS-51 single chip microcomputer are allocated to the high 128 byte unit of internal RAM. There are 22 special function registers in total, of which 21 can be accessed. Except the units occupied by registers, the remaining units can no longer be used by users, Instead, it is reserved by the system and used in later extended design<
Introction to main SFR:
program pointer register PC (program counter)
16 bit, accessible program memory space 64K, the user can not directly modify the value of the register with instructions, but the execution of transfer, call, return and other instructions can cause the change of PC value
accumulator A:
ACC is the main place of arithmetic and logic operation, the storage place of operation results, the transfer station of data transmission, and can also be used for index addressing. The frequency of use of this register is very high, and its use is very important
register B: mainly used with ACC to complete multiplication and division< PSW (program status word):
CY
AC
F0
RS1
rs0
ov
/
P
Cy: carry or borrow flag bit
AC: auxiliary carry flag bit
F0: user flag bit
rs1rs0: general register group selection bit
ov: overflow flag bit Log bit
P: parity flag bit
data pointer dptr: 16 bit data pointer, which can be divided into two 8-bit registers (DPL, DPH), mainly used to access the address register of the external data space and the table access of the program memory<
addressing problem of special function registers:
SFR can only use direct addressing mode by byte access. Specific usage examples are as follows:
mov P0, # 55h
mov 80h, # 55h
the functions and instruction codes of these two instructions are exactly the same, That is to say, the special function register can be accessed by the name or address of the register. Here 80h is the register address of port P0
bit access of special registers: there are 11 special registers that can be accessed bit by bit. The corresponding bits of these special function registers have corresponding bit addresses. Examples of accessing these bits are as follows:
CLR 80h
CLR p0.0
the functions of these two instructions are the same, but the representation methods are different, That is to say, the specific bit can be accessed by the bit address of the corresponding bit or by the name of the bit, while other bits in the register are not affected
3 The stack and its operation of MCS-51
the main function of the stack is to protect breakpoints and program sites
save user data
operation rules of the stack: first in, last out
specific operation of the stack:
creation of the stack: usually the stack pointer points to the user's RAM area ring initialization
operation of the stack: push direct_ address SP+1 → SP,(direct_ Address) → stack top unit
stack exit operation: pop direct_ addree The content of the top unit of the stack → (direct)_ 4. The allocation and use of ROM space of MCS-51 single chip microcomputer
> 0000H -- 0002h: program entry address
> 0003h -- 000ah: INT0 entry address< 000BH -- 0012h: timer0 interrupt entry address<
> 0013h -- 001ah: INT1 entry address:
> 001bh -- 0022h: Timer1 interrupt entry address< 0023h -- 002ah: serial port interrupt entry address< 002bh-ffffh: allocated by users< Summary:
ROM space:
> internal 4KB (0000H -- 0fffh) + external 60kb (1000h-ffffh) = 64KB (EA = 1)< External 64KB (0000h-ffffh) (EA = 0)<
RAM space:
> internal RAM: 00h-ffh (independent)< External RAM: 0000h-ffffh (independent of internal RAM)< Requirements: be familiar with the structure of MCS-51 parallel port and master the main functions of each parallel port< (1) port P0 is used as I / O port: MOV instruction, MUX to / Q, T1 stop
(1) port P0 is used as output: output latch, OC gate output
(2) port P0 is used as input: the read in state is not necessarily the same as the current register state, To input the status of the external pin, write high level to the corresponding pin first, and turn off T2< (2) port P0 is used as address / data bus: MOVC and MOVX instructions, MUX calls to a / D line
]. Port P0 is used as bus read: output address lower 8 bits first, then output data
]. Port P0 is used as bus write: output address lower 8 bits first, then input data
(2) structure of port P2
(1) P2 is used as a general-purpose I / O port
C = 0, MUX is connected with Q
output is pulled up internally and output is locked< (2) P2 port
9. Hello! According to your description, let me give you an answer! 1. The code is written in the internal flash. 2. It can be saved in flash. 3. On chip flash is organized in the form of page, and will not cover the program code. Hope to help you, if satisfied, please remember to adopt Oh~~~
Hot content