Can I see my files in the archives center

1. Hello: can't you. According to the regulations, personal files can only be accessed by the relevant functional departments on business. I and other indivials are not allowed to access the files without permission. It is even more illegal to disclose the file information. It is suggested that after you find the place where the archives are stored, you should report to the competent unit of the place where the archives are stored, and finally you can report the case to the court.

2. No, it's much cheaper than other places

3.

From Tianjin station to Tianjin European trade mall, you can take bus No.
461
→
677
bus No.
for delivery; It's 21.32 km
please look at the route<
Tianjin station
walk 619 meters

1. Walk 367 meters to the west, turn left

2. Walk 160 meters to the southwest, turn left back

3. Walk 92 meters to Tianjin station
461 Road (North Square of West Station - Hangu central station)
get on the train at Tianjin station
3 stops: Huabei hospital, cuifu new village Get off Tianjin No.8 Middle School
677 (Liyuan Community Airport Economic Zone bus stop)
get on Tianjin No.8 Middle School
7 stops: get off at Mingzhuang, zhaozhuangzi, airport Auto Park, East Road of Auto Park, xisan, airport investment service center, science and technology building
walk 427 meters
1, walk 72 meters, turn right

2, walk 57 meters, After crossing the road, turn right and back to enter the Central Avenue

3. Walk west along the fourth West Road for 200 meters, turn left

4. Walk south for 37 meters, turn right

5. Walk west for 62 meters to reach the destination
Tianjin European trade mall

4. Implementation of block cipher algorithm in FPGA chip based on SOC
1 Introction:

the at94k series chips proced by ATMEL company in the United States are manufactured in ATMEL 0.35 5-layer metal CMOS process. It is based on SRAM FPGA and ATMEL 8-bit RISC AVR microcontroller. In addition, the device also includes extended data and program SRAM and device control and management logic. Figure 1-1 shows the internal structure of ATMEL's fpslic<

Figure 1-1 internal structure of fpslic

at94k is embedded with AVR core, ATMEL's fpslic programmable SOC is embedded with high-performance and low-power 8-bit AVR microcontroller, at most 36KB SRAM, 2 UARTS, 1 two-wire serial interface, 3 timers / counters, 1 8 8 multiplier and a real-time clock. By using single cycle instruction, the operation speed is up to 1mps / MHz, so that users can fully optimize the system power consumption and processing speed. AVR core is based on enhanced RISC structure, which has rich instruction system and 32 general working registers. All the general registers are connected with ALU; In addition, two independent registers are allowed to be accessed when a single instruction is executed in a clock cycle. This structure makes the code more efficient, and the data throughput is 10 times higher than that of the traditional CISC microprocessor at the same clock frequency. AVR executes programs from on-chip SRAM. Because AVR running code is stored in SRAM, it can provide relatively large throughput, so it can work in burst mode. In this mode, AVR is in low-power standby mode most of the time, and can carry out high-performance processing in a very short time. The average power consumption of microprocessor in burst mode is much lower than that in low frequency mode. The standby current of fpslic is less than 100, and the typical working current is 2-3ma / MHz. When the system is powered on, SRAM and AVR program configured by FPGA can be automatically loaded in the system programmable serial memory at17 through ATMEL<

2 design and implementation of fpslic Hardware:

2.1 hardware implementation block diagram

Figure 2-1 system hardware implementation block diagram

Figure 2-1 is the hardware block diagram to realize encryption algorithm. The computer is connected with UART0 of fpslic through its serial port to transmit and receive data. Fpslic waits to receive the information from the host through the communication port of AVR, processes the data through the internal download program, and finally transmits it back to the host. In Figure 2-1, FPGA is a counter, which counts from 0 as soon as it is powered on, and generates an AVR interrupt with carry output signal, that is, the carry output signal RCO is connected to the interrupt signal inta0 of AVR. When AVR receives the interrupt generated by the carry signal of the counter, it executes the interrupt service program (ISR) of inta0. During this period
, AVR will count the number of times generated by inta0 and put it on the 8-bit avr-fpga data bus. At this time, AVR's write enable signal (FPGA's awe signal end) and FPGA's I / O select0 signal (FPGA's load signal end) will be triggered, and the data will be loaded into the counter from avr-fpga data bus. Each pole of the nixie tube is connected to the programmable port on the experimental board and used to display data through pin configuration. The LED indicator is in the D port of AVR I / O output, which directly displays the data through the command portd. The clock of FPGA is selected from the clock of AVR MCU by gclk5. Taking des data encryption as an example, the simulation results show that the rate of DES encryption is 57.024 kbit / s, which is higher than the maximum rate of 19.2kbit/s of serial port, so it can encrypt data in real time< A typical fpslic design usually includes the following steps:

1

2. Create an AVR software simulation program file in advance

3. Build a FPGA hardware simulation program file in advance< 4. Setting and running avr-fpga interface design

5. Run pre layout verification of CO simulation before layout (this step is optional)

6. Run Figaro IDs for FPGA layout and wiring

7. Run the co simulation POS layout verification after layout (this step is optional)

8. Device programming data download and experimental verification

let's take des data encryption as an example. (the new project name is lab1.apj, the AVR simulation program file is dejiami.asm, and the FPGA hardware simulation program is count.vhdl)<

2.2 compile AVR simulation program software

(the above program code is the whole simulation program framework, the most important thing is to initialize the interface and set the sending and receiving parts, 2.3 device programming and test verification

1. Connect the 25 pin end of the download cable atdh2225 from the parallel port of the computer, and insert the 10 pin flat wire into the J1 plug of atstk94 experimental board. The red line of the download cable is connected to the first pin of the J1 plug

2. Because it needs to communicate with the computer serial port, it is necessary to make a serial port connection cable. The connection relationship of the nine pin connection cable is shown in Figure 2-2 below. One end of the cable is connected to any serial port of the computer, and the other end is connected to UART0 on the experimental board. The connecting cable only needs to connect three wires. The 2 end of UART0 is connected to the sending end of fpslic, so it is connected to the 2 end of serial port (data receiving end) of computer. The 3-terminal of UART0 is connected to the receiving terminal of fpslic, so it is connected to the 2-terminal of serial port (sending data terminal) of computer< br />
&n
bsp; Figure 2-2 serial port communication connection indication diagram

3. Select 4MHz clock, that is, set jp17 close to the inside of the board on the experimental board, and do not connect jp18, that is, unplug its connection jumper

4. Plug the DC 9V power connector into the power socket P3 of atstk94 experimental board

5. Set the switch SW10 on the test board to prog position. Switch SW10 has prog and run connections. In the programming position, the user can download the cable and the program software CPS to program the fpslic data stream file generated by system designer to the configuration memory. In the run position, the fpslic device will load the data stream file and run the design

6. Turn on the power switch sw14, that is, adjust it to the on position. At this time, the power LED (red) on the test board lights up, indicating that the test board has been powered on. In this way, the hardware is connected and waiting for the next data download

7. Click OK to generate the data stream file, which will be downloaded to the configuration memory of atstk94 experimental board. At this time, ATMEL's at17 configuration programmable system (CPS) window will be opened, as shown in Figure 2-3 below, and the device will be programmed automatically

figure 2-3 fpslic control register setting dialog box

select / P partition, program and verify from an ATMEL file in the process drop-down list box. Select at40k / cypress in the family drop-down list box and at17lv010 (a) (1m) in the device drop-down list box. The rest adopt the default value of the system. Then click the start proce button, if the cable and other hardware settings are correct, then the program will be downloaded to the experimental board

8. Turn the switch SW10 to run and open the serial port debugging program accesspot129. For accessport129, the serial port is COM1 (set according to the computer port selected by the user), the baud rate is 9600, the check bit is none, the data bit is 8, the stop bit is 1, and the serial switch is on

3 test results:

in Figure 3-1, the following box is the 64 bit plaintext to be input (the plaintext input in the program is 0123456789abcdef). After all the 64 bit data are input, click the send button, and the encrypted ciphertext (85e813540f0ab405) encrypted by DES algorithm will be displayed on the data receiving end above the software. The results of hardware implementation are completely consistent with the actual
simulation results. At the same time, the final encrypted data is also displayed through the digital tube. So far, the whole hardware test is over

Figure 3-1 the result chart of the serial debugging software of accesspot

from the above serial debugging software, we can see that the simulation of DES algorithm is correct and can be applied in practice. In the same way, we can use the above methods to achieve DES decryption and AES and other packet encryption and decryption.

5. Metro Line 3 to line 2

6. There are no direct buses
two options
take No.10 bus to Jiangong primary school and get off the bus
after getting off the bus, continue to walk eastward
about five minutes to see the Pacific Insurance Building, turn south and walk for another five minutes, the left side is
or take No.4 bus to Henan International Trade, and then take No.14 bus to Jinshan Jiayuan and get off the bus
diagonally opposite

7. There are four high-speed railway stations in Tianjin, and the general situation is as follows:
1. Tianjin South Station, next to Jingfu branch line of Jinjin expressway, Zhangjiawo Town, Xiqing District, Tianjin. Beijing Shanghai high-speed railway main line interval station, South to Shanghai Hongqiao and Qing, north to Beijing south station
2. Tianjin west railway station, address: West Road, beiyingmen, Hongqiao District, Tianjin (near Dahutong). Beijing Shanghai high-speed rail connecting line lead-in station, South to Shanghai Hongqiao and Qing, at the same time connecting the Beijing Shanghai existing line common speed
3. Tianjin station, address: No.1 Xinwei Road, Hebei District, Tianjin (the intersection of Xinwei road and Haihe East Road, Hebei District). The Beijing Tianjin Intercity access station is also connected with the general speed of Tianjin Shanshan line
4. Tanggu station, address: beside the overpass of Chezhan North Road in Binhai New Area (near Tanggu Experimental Primary School). Beijing Tianjin Intercity extension line access station, at the same time, connecting to the Tianjin mountain line common speed;

8.

Snapdragon 865 and snapdragon 765 support all modes of 2G / 3G / 4G / 5G, sub-6ghz / millimeter wave, TDD / FDD, NSA / SA, DSS (dynamic spectrum sharing) and carrier aggregation, with download speed up to 3.7gbps. At the same time, they will continue to improve in photography, artificial intelligence and games, including supporting 4K HDR video shooting and integrating the fifth generation AI engine

snapdragon 865 is more outstanding than the previous generation in CPU, GPU, AI and camera. Snapdragon 865 platform has twice the AI computing performance before, and even supports the image computing capacity of up to 200 million pixels per second. It can support 8K 30fps video recording. The flagship snapdragon 865 mobile platform and snapdragon x55 modem and RF system are the world's leading 5g platforms capable of supporting global 5g deployment, which will provide connectivity and performance for the next generation of flagship terminals

9.

56W

snapdragon 865 still adopts TSMC 7Nm process (snapdragon 765 series uses Samsung 7Nm process), CPU is based on the latest kryo 585 architecture of Qualcomm, and also adopts eight core design, including a 2.84ghz cortex-a77 core, three 2.42ghz a77 middle cores and four 1.8GHz A55 small cores

although the frequency of the main core is lower than that of the snapdragon 855 +, thanks to the new technology, Qualcomm said that its overall performance has been improved by 25%, and its power consumption has also been reced by 25%. GPU part of the snapdragon 865 is equipped with the latest Adreno 650, the official said that its performance is 20% higher than the previous generation, and its power consumption is also reced by 35%

extended data:

precautions:

geekbench 5.0.2 canceling memory points and further improving the proportion of integers are more helpful to reflect the integer performance that affects daily use, which also makes geekbench's load heavier, which is more obviously reflected in the multi-core performance, that is, the single core score is high, but the multi-core score is low

is usually caused by processor heating, or multi-core performance instability, is caused by overheating. The 25% increase in energy efficiency of Xiaolong 865 is also an important reason for the obvious increase in multi-core score