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1. Classmate, you have g bedrock = = bedrock is the lowest square in my world, which is equivalent to the protective layer. Bedrock is invincible = = you can't destroy it, you can't excavate it, you can't get it, unless you are creative, you can take it from the item list. Under bedrock is void. Once you fall, you will die. No matter whether you survive or create it[ No one answered such a simple question as NIMA

2. CAS means column address strobe or column address select. CAS controls the interval time from receiving a command to executing a command, usually 2, 2.5, 3 clock cycles. In the whole memory matrix, CAS manages physical addresses by column address, so on a stable basis, the lower the value of this very important parameter, the better. The process is as follows: the memory array is divided into rows and columns. When the command request arrives in the memory, the first trigger is the tra s (active to precharge delay). After the data is requested, it needs to be pre charged. Once the tra s is activated, the RAS starts to search for the address in half of the physical address. After the row is selected, the tRCD is initialized, and finally the exact address is found through CAS. The whole process is first addressing and then column addressing. From the beginning of CAS to the end of CAS, we are talking about the delay of CAS. Because CAS is the last step of addressing, it is the most important memory parameter. Cl (CAS latency): is the delay time of CAS, which is the response time of longitudinal address pulse. It is also one of the important marks to measure the memory supporting different specifications at a certain frequency. Memory is responsible for providing the CPU with the original data needed for the operation. At present, the CPU runs faster than the memory data transmission speed, so in many cases, the CPU needs to wait for the memory to provide data, which is often called "CPU waiting time". The slower the memory transfer speed, the longer the CPU waiting time, and the greater the impact on the overall performance of the system. Therefore, fast memory is one of the keys to improve CPU efficiency and overall performance. In the actual work, no matter what type of memory, before the data is transmitted, the sender must spend a certain amount of time waiting for the response of the transmission request. Generally speaking, before the transmission, the two sides must carry out the necessary communication, which will cause a certain delay in the transmission. To some extent, the CL setting reflects the waiting time of the memory from the CPU receiving the instruction to read the memory data to the formal start of reading the data. It is not difficult to see that with the same frequency of memory, the low Cl setting has more speed advantage. In the white paper of PC100 memory technology of Intel company, it is pointed out that "the memory chip conforming to PC100 standard should work stably at the frequency of 100MHz under the condition of CAS latency (hereinafter referred to as CL) = 2." CL = 2 means that the delay time of reading data from memory is two clock cycles when CL = 3. The delay time of memory reading data should be three clock cycles. Therefore, the difference between "2" and "3" is not limited to "1", but one clock cycle. For the same kind of memory working at the same frequency, setting CL to 2 will get better performance than 3 (of course, your memory must support CL = 2 mode). In order to make the motherboard set the CAS delay time correctly for the memory, the memory manufacturers record the recommended CAS delay time under different operating frequencies on an EEPROM on the memory PCB, which is what we call SPD. When the system is powered on, the main board BIOS will automatically detect the information in SPD and finally determine whether to run with CL = 2 or Cl = 3. The above is just to establish a basic CL concept for you, but in fact, the basic factors of memory latency are definitely more than these. Memory latency has a special term called latency. To understand the delay vividly, we might as well treat the memory as an array storing data or an excel table. To determine the position of each data, each data is marked by row and column sorting numbers. After the row and column serial numbers are determined, the data will be unique. When the memory is working, to read or write some data, the memory control chip will first transmit the column address of the data, and the RAS signal (row address strobe) will be activated. Before converting to the row data, it needs to go through several execution cycles, and then the CAS signal (column address strobe) will be activated. Several execution cycles between RAS signal and CAS signal are RAS to CAS delay time. It also needs several execution cycles after CAS signal is executed. This execution cycle is about 2 to 3 cycles in SDRAM using standard PC133; DDR ram has four to five cycles. In DDR, the real CAS latency is 2 to 2.5 execution cycles. The time of RAS to CAS depends on the technology, about 5 to 7 cycles, which is also the basic factor of delay. Memory with a lower CL setting has a higher advantage, which can be shown by the total latency. There is a formula to calculate the total delay time of memory. The total delay time = system clock cycle × CL mode number + access time (TAC). First of all, let's understand the concept of access time (TAC). TAC is the abbreviation of access time from CLK, which refers to the maximum number of input clocks at the maximum CAS delay. It is in nanoseconds, which is completely different from the memory clock cycle, although it is in nanoseconds. Access time (TAC) represents the time of reading and writing, while clock frequency represents the speed of memory

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3.

CL reaction time is another indicator of memory balance. CL is the abbreviation of CAS latency, which refers to the delay time required for memory to access data. In short, it is the response speed of memory after receiving instructions from CPU. The general parameter values are 2 and 3. The smaller the number, the shorter the reaction time

in the early PC133 memory standard, this value was set at 3, while in the new Intel specification, the reaction time of CL was required to be 2. In this way, to a certain extent, the requirements for the chip and PCB assembly process of memory manufacturers were relatively high, and better quality was ensured. Therefore, in the purchase of brand memory, this is an indispensable factor

extended data:

CL = 2 means that the delay time of reading data from memory is two clock cycles when CL = 3. The delay time of memory reading data should be three clock cycles. Therefore, the difference between "2" and "3" is not limited to "1", but one clock cycle

for the same kind of memory working at the same frequency, setting CL to 2 will get better performance than 3. In order to make the motherboard set the CAS delay time correctly for the memory, the memory manufacturers record the recommended CAS delay time under different operating frequencies on an EEPROM on the memory PCB, which is SPD. When the system is powered on, the main board BIOS will automatically detect the information in SPD and finally determine whether to run with CL = 2 or Cl = 3

4. Cl (CAS latency): is the delay time of CAS, which is the response time of longitudinal address pulse. It is also one of the important marks to measure the memory supporting different specifications at a certain frequency
the memory is responsible for providing the CPU with the raw data needed for the operation. At present, the CPU runs faster than the memory, and the data transmission speed is much faster. Therefore, in many cases, the CPU needs to wait for the memory to provide the data, which is often called "CPU waiting time". The slower the memory transfer speed, the longer the CPU waiting time, and the greater the impact on the overall performance of the system. Therefore, fast memory is one of the keys to improve CPU efficiency and overall performance
in actual work, no matter what type of memory, before the data is transmitted, the sender must spend a certain amount of time waiting for the response of the transmission request. Generally speaking, the sender and the receiver must communicate before transmission, which will cause a certain delay of transmission. To some extent, the CL setting reflects the waiting time of the memory from the CPU receiving the instruction to read the memory data to the formal start of reading the data. It is not difficult to see that with the same frequency of memory, the low Cl setting has more speed advantage
the above is just to establish a basic concept of Cl, but in fact, the basic factors of memory latency are definitely more than these. Memory latency has a special term called latency. To understand the delay vividly, we might as well treat the memory as an array storing data or an excel table. To determine the position of each data, each data is marked by row and column sorting numbers. After the row and column serial numbers are determined, the data will be unique. When the memory is working, to read or write some data, the memory control chip will first transmit the column address of the data, and the RAS signal (row address strobe) will be activated. Before converting to the row data, it needs to go through several execution cycles, and then the CAS signal (column address strobe) will be activated. Several execution cycles between RAS signal and CAS signal are RAS to CAS delay time. It also needs several execution cycles after CAS signal is executed. This execution cycle is about 2 to 3 cycles in SDRAM using standard PC133; DDR ram has four to five cycles. In DDR, the real CAS latency is 2 to 2.5 execution cycles. The time of RAS to CAS depends on the technology, about 5 to 7 cycles, which is also the basic factor of delay
CL has a higher advantage by setting lower memory, which can be shown by the total latency. There is a formula to calculate the total delay time of memory. The total delay time = system clock cycle × CL mode number + access time (TAC). First of all, let's understand the concept of access time (TAC). TAC is the abbreviation of access time from CLK, which refers to the maximum number of input clocks at the maximum CAS delay. It is in nanoseconds, which is completely different from the memory clock cycle, although it is in nanoseconds. Access time (TAC) represents the time of reading and writing, while clock frequency represents the speed of memory
take an example to calculate the total delay time. For example, the access time of a ddr333 memory is 6ns, and the memory clock cycle is 6ns (DDR memory clock cycle = 1x2 / memory frequency, DDR400 memory frequency is 400, then the clock cycle is 6ns). If we set CL to 2.5 in the BIOS of the motherboard, the total delay time is 6ns x2.5 + 6ns = 21ns. If CL is set to 2, the total delay time is 6ns x2 + 6ns = 18ns, which reces the time by 3ns
in terms of the total delay time, the CL value plays a key role. Therefore, users who have high requirements for the system and like overclocking usually like to buy memory with low Cl value. At present, in addition to improving the DDR performance by increasing the memory clock frequency, memory granule manufacturers have considered further recing the CAS delay time to improve the memory performance
however, it does not mean that the lower the CL value, the better the performance, because other factors will affect this data. For example, the cache of the new generation processor is more efficient, which means that the processor reads less data directly from memory. Moreover, column data will be accessed more often, so the probability of RAS to CAS is high, and the reading time will increase. Finally, sometimes a large amount of data will be read at the same time. In this case, the adjacent memory data will be read out at one time, and the CAS delay time will only occur once
when choosing to purchase memory, it is better to choose the memory with the same cl setting, because the system will run at a slower speed when the memory with different speeds is mixed in the system, that is, when the memory with cl2.5 and Cl2 is inserted in the host at the same time, the system will automatically make both memories work in cl2.5 state, resulting in a waste of resources.